NMC9306EN ,256-Bit Serial Electrically Erasable Programmable MemoryNMC9306
National
Semiconductor
NMC9306 256-Bit Serial Electrically Erasable
Programmable ..
NMC9306N ,256-Bit Serial Electrically Erasable Programmable MemoryGeneral Description
The NMC9306 is a 256-bit non-volatile sequential access
memory fabricated u ..
NMC9307EN ,Vcc=5V+/-10%, 256-bit serial electrically erasable programmable memoryElectrical Characteristics
Lead Temperature (Soldering, 10 sec.) 300°C
ESD Rating 2000V
Note ..
NMC9346 ,1024 Bit Serial Electrically Erasable Programmable MemoryBlock Diagram
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NMC9346EN ,+6 to -0.3V; 1024-bit serial electrically erasable programmable memoryBlock Diagram
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NMC9346N ,+6 to -0.3V; 1024-bit serial electrically erasable programmable memoryFeatures
The NM09346 Is a 1024-bit non-volatile, sequential I Designed for 40,000 erasé/write cy ..
OM4068H ,LCD driver for low multiplex ratesGENERAL DESCRIPTION1⁄3The OM4068 is a low-power CMOS LCD driver, designed• 32 segment driversto dri ..
OM4068H/2 ,OM4068; LCD driver for low multiplex rates
OM4085T/F1 ,OM4085; Universal LCD driver for low multiplex rates
OM5193H ,Disk drive spindle and VCM with servo controller
OM5202FBB ,ROMless 8-bit microcontroller
OM5604 ,Multimedia radio tuner
NMC9306EN-NMC9306N
256-Bit Serial Electrically Erasable Programmable Memory
National
Semiconductor
NMC9306 256-Bit Serial Electrically Erasable
Programmable Memory
General Description Features
The NMC9306 is a 256-bit non-volatile sequential access Low cost
memory fabricated using advanced floating gate N-channel Single supply operation (5V i 10%)
E2PROM technology. It is accessed via the simple TTL compatible
MICROWIRETM serial interface and is designed for data 16x16 serial read/write memory
.st..orairr and/ou: timing applications: The dawge contams Pf MICROWIHE compatible serial I /O
bits of pad/writ? memory fivitmd.it.1.to 16 registers. of 16 bits Compatible with COP4OO processors
each. Each register can be serially read or written by a
COP400 series controller. Written information is stored in a Low stangby power .
floating gate cell with at least 10 years data retention and Non-volatile erase and write
can be updated by an erase-write cycle. The NM09306 has Reliable floating gate technology
been designed to meet applications requiring up to 4X104 Designed for 40,000 erase/write cycles
erase/write cycles per register. A power down mode reduc-
es power consumption by 70 percent.
NMC9306
Block Diagram
GENERATOR
32 E PROM
l/tti (16x16)
annnsss Pin Names
LATCHES n/w AMPS
CS Chip Select
Iii SK Serial Data Clock
DI Serial Data Input
REGISTER no DO Serial Data Output
(17 sum cut
Vcc Power Supply
GND Ground
INSTRUCTION
REGISTER cut
(9 ans)
INSTRUCTION
DECODE.
CONTROL
GENERATORS
TL/D/5029-1
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Connection Diagram
Dual-ln-Llne Package (N)
TL/D/6029-10
See NS Package Number NOSE
Ordering Information
so Package (M8)
SK-' 2
ty-- 3
Top Vlew
TL/D/5029-11
See NS Package Number MOBA
Cotttrttttrttlttl Temperature Range (0''C to + 70°C)
Vcc = SV , 10%
Order Number Dovlco Marking
NMC9306N NMC9306N
NMC9306M8 9306
Extended Temperature Range (-4WC to + 85°C)
Vcc == 5V i 10%
Order Number
Device Marklng
NMC9306EN
NMC9306EM8
NMC9306EN
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QOSGOWN
NMC9306
Absolute Maximum Ratings
Voltage Relative to GND
Ambient Storage Temperature
Lead Temperature
(Soldering, 10 seconds)
ESD rating
+ 6V to -0.3V
-65"C to + 125''C
Operating Conditions
Ambient Operating Temperature
NM09306/COP494 0°C to + 70''C
NM09306E - 4ty'G to f 85''C
Positive Supply Voltage 4.5V to 5.5V
Note: Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicat-
ed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Electrical Characteristics Vcc = 5V i10% unless otherwise specified
Parameter Part Number Conditions Min Typ Max Units
Operating Voltage (Vcc) NMC9306, NMG9306E 4.5 5.5 V
Operating Current (lcc1) NM09306 Vcc = 5.5V, CS = 1 10 mA
NMC9306E Vcc = 5.5V, CS == 1 12 mA
Standby Current (Iccg) NMC9306 Vcc -.-- 5.5V, cs = 0 3 mA
NM09306E Vcc = 5.5V, cs = o 4 mA
InputVoltage Levels
" NM09306 -0,1 0.8 V
VIH 2.0 Vcc + 1 V
" NMCSSOSE -0.1 0.8 V
VIH 2.0 VCC + 1 V
Output Voltage Levels NMC9306, NMC9306E
VOL IOL = 2.1 mA 0.4
VOH IOH = -400 psA 2.4 f . V
Input Leakage Current NM09306, NMC9306E VIN = 5.5V 10 “A
Output Leakage Current NMCQSOS, NMCQSOSE VOUT = 5.5V, GS = 0 10 pA
SK Frequency NM09306 0 250 kHz
SK HIGH TIME tSKH (Note 2) 1 us
SK LOW TIME tSKL (Note 2) 1 “5
SK Frequency NMC9306E 0 kHz
SK HIGH TIME tSKH (Note 2) 1 250 ps
SK LOW TIME tSKL (Note 2) 1 ps
Input Set-up and Hold Times NM09306, NMC9306E
CS tcss 0.2 ps
tCSH 0 #8
DI Us 0.4 )LS
10m 0.4 ps
Output Delay NMC9306, NM09306E th. = 100 pF
DO tpD1 VOL = 0.8V, VOH = 2.0V 2 gs
{poo " == 0.45V, VIH --- 2.4V 2 [.LS
Erase/Write Pulse Width NMC9306, NMC9306E 10 30 m s
(EM) (Note 1)
CS Low Time NMC9306, NMC9306E 1 s
(tcs) (Note 3) "
Note I.. tE/w measured to rising edge of SK or CS, whichever occurs last.
Note 2: The SK frequency spec. specifies a minimum SK clock period of 4 #5. therefore in an SK clock cycle, ism + tst must be greater than or equal to 4 us.
B.g, it tSKL = 1 us then the minimum tSKH = a MS in order to meet the SK frequency trpmritication.
Note 3: GS must be brought low for a minimum of 1 us (tcs) between consecutive instruction cycles.
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Functional Description
The NMC9306 is a small peripheral memory intended tor
use with COPSTM controllers and other non-volatile memory
applications. Its organization is sixteen registers and each
register is sixteen bits wide. The input and output pins are
controlled by separate serial formats. Seven 10-bit instruc-
tions can be executed. The instruction format has a logical 0
as a start bit, followed by a logical I, four bits as an op code,
and tour bits of address. An SK clock cycle is necessary
after CS equals logical 0 followed by a logical 1 before the
instruction can be loaded. The on-chip programming-volt-
age generator allows the user to use a single power supply
(Vcc). Only during the read mode is the serial output (DO)
pin valid. During all other modes the DO pin is in
TRI-STATE', eliminating bus contention.
The read instruction is the only instruction which outputs
serial data on the DO pin. After a READ instruction is re-
ceived, the instruction and address are decoded, followed
by data transfer from the memory register into a 16-bit seri-
al-out shift register. A dummy bit (logical 'o') precedes the
16-bit data output string. Output data changes are initiated
by a low to high transition of the SK clock.
ERASE/WRITE ENABLE AND DISABLE
Programming must be preceded once by a programming
enable (EWEN) instruction. Programming remains enabled
until a programming disable (EWDS) instruction is executed.
The programming enable instruction (EWEN) is needed to
keep the part in the enable state if the power supply (VCC)
noise falls below operating range. The programming disable
instruction is provided to protect against accidental data dis-
turb. Execution of a READ instruction is independent of both
EWEN and EWDS instructions.
ERASE (Note 4)
Like most E2PROMS, the register must first be erased (all
bits set to I's) before the register can be written (certain bits
Instruction Set
set to O's). After an ERASE instruction is input, CS is
dropped low. This falling edge of CS determines the start of
programming. The register at the address specified in the
instruction is then set entirely to I's. When the erase/write
programming time (tE/w) constraint has been satisfied, CS
is brought up for at least one SK period. A new instruction
may then be input, or a low-power standby state may be
achieved by dropping CS low.
WRITE (Note 4)
The WRITE instruction is followed by 16 bits of data which
are written into the specified address. This register must
have been previously erased. Like any programming mode,
erase/write time is determined by the low state of CS fol-
lowing the instruction. The on-chip high voltage section only
generates high voltage during these programming modes,
which prevents spurious programming during other modes.
When CS rises to VIH‘ the programming cycle ends. All pro-
gramming modes should be ended with CS high for one SK
period. or followed by another instruction.
CHIP ERASE (Note 4)
Entire chip erasing is provided for ease of programming.
Erasing the chip means that all registers in the memory ar-
ray have each bit set to a 1. Each register is then ready for a
WHITE instruction.
CHIP WRITE (Note 4)
All registers must be erased before a chip write operation.
The chip write cycle is identical to the write cycle, except for
the different op code. All registers are simultaneously writ-
ten with the data pattern specified in the instruction.
Note 4: During a programming mode (write, erase, chip erase, chip write),
SK clock is only needed while the actual instruction. Le., start bit, op
code, address and data, is being input. It can remain deactivated
during the Erase/Write pulse width (tE/w).
lnstructlon SB Op Code Address Data Comments
READ 01 10xx A3A2A1A0 Read Register A3A2A1AO
WRITE 01 01xx A3A2A1A0 D15 - D0 Write Register A3A2A1A0
ERASE 01 11xx A3A2A1A0 Erase Register A3A2A1A0
EWEN 01 001 1 XXXX Erase/Write Enable
EWDS 01 0000 XXXX Erase/Write Disable
ERAL 01 0010 XXXX Erase All Registers
WRAL 01 0001 XXXX D15 - DO Write All Registers
NMCQSOB has 7 instructions as shown. Note that MSB of any given instruction is a "I" and is viewed as a start bit in
the interface sequence. The next 8 bits carry the op code and the 4-bit address tor 1 of 16, 16-bit registers.
X is a dort't care state.
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90860WN
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NMC9306
Synchronous Data Timing
SK tSKH tSKL
0.4 #5 0.4 ps
tDIS "DIH
DI VALID
0.2 #5 I "CSH
tcss 0.0 MS
2 p3 2 p8
tP00 th
'This is the minimum SK period and is 5;; for NMCQGOGM
TL/D/5029- 1 3
ng Diagrams
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Timing Diagrams (Continued)
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NMC9306
Instruction Timing (Continued)
5* F1 ['1 LJ LT U [J Li [J L
mmfii‘s °‘ / ¥
ENABLE=11
DISABLE=00
TL/D/5029-17
“J_LI'I L] F'Ll W 4 L
(mm33 “1/ { t___J/____—____-_'
1"’/////////////////////////////////m XWX l1§x
TL/D/5029— 18
TL/D/5029—19
'tE/w measured to rising edge of SK or CS. whichever occurs last,
Timing Diagrams (Continued)
This datasheet has been :
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
NMC9306EM8 - product/nm09306em8?HQS=T|-nu|I-null-dscatalog-df-pf—nuII-wwe
NMC9306M8 - product/nm09306m8?HQS=Tl-null-null-dscatalog-df—pf—nuII-wwe
NMC9306EN - product/nm09306en?HQS=T|-nu|I-nulI-dscatalog-df-pf-null-wwe
NMC9306N - product/nmc9306n?HQS=T|-nu|I-nu|I-dscatalog-df-pf-nulI—wwe
