NMC27C64QE-150 ,150 ns, Vcc=5V+/-10%, 65,536-bit (8k x 8) UV erasable CMOS PROMapplications where fast turnaround, pattern experimentation
and low power consumption are importan ..
NMC27C64QE-150 ,150 ns, Vcc=5V+/-10%, 65,536-bit (8k x 8) UV erasable CMOS PROMGeneral Description
The NMC27C64 is a high-speed 64k UV erasable and elec-
trically reprogramma ..
NMC27C64QE--150 ,150 ns, Vcc=5V+/-10%, 65,536-bit (8k x 8) UV erasable CMOS PROMNMC27C64
National
Semiconductor
NMC27C64 65,536-Bit (8k x 8)
NMC27C64QE200 , 64KBit (8192 x 8) CMOS EPROM [Life-time buy]General Description
The NMC27C64 is a high-speed 64k UV erasable and elec-
trically reprogramma ..
NMC27C64QE-200 , 64KBit (8192 x 8) CMOS EPROM [Life-time buy]NMC27C64
National
Semiconductor
NMC27C64 65,536-Bit (8k x 8)
NMC27C64QE-200 , 64KBit (8192 x 8) CMOS EPROM [Life-time buy]applications where fast turnaround, pattern experimentation
and low power consumption are importan ..
OM4068H ,LCD driver for low multiplex ratesGENERAL DESCRIPTION1⁄3The OM4068 is a low-power CMOS LCD driver, designed• 32 segment driversto dri ..
OM4068H/2 ,OM4068; LCD driver for low multiplex rates
OM4085T/F1 ,OM4085; Universal LCD driver for low multiplex rates
OM5193H ,Disk drive spindle and VCM with servo controller
OM5202FBB ,ROMless 8-bit microcontroller
OM5604 ,Multimedia radio tuner
NMC27C64Q150-NMC27C64Q-150-NMC27C64Q200-NMC27C64Q250-NMC27C64Q-300-NMC27C64QE150-NMC27C64QE-150-NMC27C64QE--150-NMC27C64QE200-NMC27C64QE-200-NMC27C64QE--200-NMC27C64QM200-NMC27C64QM-200
200 ns, Vcc=5V+/-10%, 65,536-bit (8k x 8) UV erasable CMOS PROM
NMC27C64
National
Semiconductor
NMC27C64 65,536-Bit (8k x 8) UV Erasable CMOS PROM
General Description
The NMC27C64 is a high-speed 64k UV erasable and elec-
trically reprogrammabie CMOS EPROM, ideally suited for
applications where fast turnaround, pattern experimentation
and low power consumption are important requirements.
The NMC27C64 is designed to operate with a single + 5V
power supply with i5% or i10% tolerance. The CMOS
design allows the part to operate over extended and military
temperature ranges.
The NMC27064 is packaged in a 28-pin dual-in-line pack-
age with transparent lid. The transparent lid allows the user
to expose the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written electrically into the device
by following the programming procedure.
This EPROM is fabricated with NationaI's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low pow-
er consumption and excellent reliability.
Featu res
" Clocked sense amps for fast access time down to
150 ns
tt Low CMOS power consumption
- Active Power: 55 mW max
- Standby Power: 0.55 mW max
II Performance compatible to NSCBOOTM CMOS micro-
processor
II Single 5V power supply
Extended temperature range (NMC27C64QE), -40oC
to +65°C. and military temperature range
(NMC27C64QM), -55''C to +125''C, available
Pin compatible with NMOS 64k EPROMs
Fast and reliable programming
Static operation-no clocks required
TTL, CMOS compatible inputs/outputs
TRi-STATE® output
Optimum EPROM for total CMOS systems
Manufacturer's identification code for automatic pro-
gramming control
Block Diagram
DATA OUTPUTS h-th
Vcc o-r
VPP o--.
OUTPUT EN ABLE
AND CHIP
ENABLE LOGIC
DECODER
ADDRESS
INPUTS
DECODER
OUTPUT
BUFFERS
Y EATING
85,536-311'
CELL MATRIX
e----"------,
Pin Names
A0 -A1 2 Addresses
UE Chip Enable
W Output Enable
00-07 Outputs
m Program
NC No Connect
TL/D/MM - 1
Connection Diagram
2rcsr22rc2ss2rm2tr2rcs22rcei NMCNCMQ 27C16 27C32 27C128 270256 27C512
27512 27256 27128 2732 2716 DuaI-In-Llne Package 2716 2732 27128 27256 27512
A15 VPP VPP V" --, l " lltt; Vcc Vcc Vcc
A12 A12 A12 Me-t 27 Pm PGT3 A14 A14
A7 A7 A7 A7 A7 A7 - 3 N - NC Vcc Vcc A13 A13 A13
A6 A6 A6 A6 A6 M - 4 25 " A8 A8 A8 A8 A8
A5 A5 A5 A5 A5 M - 5 " - " A9 A9 A9 A9 A9
A4 A4 A4 A4 A4 M _ 5 23 - MI Vpp A11 A11 A11 A11
A3 A3 A3 A3 A3 A3 -1 7 t? - 6t tTi? CE/vpp UE CE 'x/tn
A2 A2 A2 A2 A2 M -- 8 21 - MO A10 A10 A10 A10 A10
A1 A1 A1 A1 A1 M T 9 20 - et CE/FCW tTE CE tX/PWM CE
A0 A0 A0 A0 A0 M - IO 19 - th Or 07 o, o, 07
00 00 00 00 th h - 11 18 - Os 06 ths Os 06 05
ch O1 O1 o, O1 th - 12 " L Os Os Os Os ths Os
O2 O2 02 02 02 o, - 13 18 '--h 04 04 04 04 04
GND GND GND GND GND (1tt0-- " 15 - 0: th 03 O3 03 03
TL/D/8634-2
Note: Socket compatible EPROM pin configurations are shown in the blocks adiacenl to the NM027CS4 pins.
Order Number NMC270640
See NS Package Number J28AQ
Commercial Temp Range (0°C to + 70°C)
Vee = w 15%
Parameter/Order Number Access Time (ns)
NMC27C64t215 150
Vcc = 5V se 10%
Parameter/Order Number Access Time (ns)
NMC27C64t2150 150
NMC27C64C200 200
NMC27C64Q250 250
NMC27C64Q300 300
Extended Temp Range ( - 40°C to + 85°C)
Vcc = SV t10%
Parameter/Order Number Access Time (ns)
NMC27C64QE150 150
NMC27C64QE200 200
Mllltary Temp Range (-55'C to + 125°C)
Vcc = 5V 110%
Parameter/Order Number
Access Time (ns)
N MC27C64CM200
NMC27C64QM250
NOTE: For plastlc DIP requirements please refer to NM027064N data sheet.
VSOLZOWN
Capacitance TA = +25°C,f = 1 MHz (Note 2)
Symbol Parameter Conditions Typ Max Units
CIN InputCapacitance VIN = 0V 6 8 pF
COUT Output Capacitance Vour = 0V 9 12 pF
AC Test Conditions
Output Load 1 ITL Gate and Timing Measurement Reference Level
Ct. == 100 pF (Note 8) Inputs 0.8V and 2V
Input Rise and Fall Times s5 ns Outputs 0.8V and 2V
Input Pulse Levels 0.45V to 2.4V
AC Waveforms (Notes a & 9)
2.0V ' J J X
ADDRESSES 0.8V c, ADDRESSES VALID f r
- 2.0V N e-'"-""''-
CE 0.8V r r /
u--- tcs ---- pr- kr -
(NOTES 4, 5)
- 2.0V \
0: 0.iN r r /
tos J - tor ---
(NOTE 3) r r (NOTES 4, 5)
2.0V Hi-Z , J "1.2
OUTPUT 0.8V VALID OUTPUT r r , '
J J ..
tacc V-
(NOTE 3) tor,
TL/D/8634-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: UE may be delayed up to 1Acc - tog after the falling edge of CE without impacting tacc.
Note & The top and top compare level is determined as follows:
High to TRI-STATE, the measured Vom (DC) - 0.10V;
Low to TRMOATE, the measured Von (DC) + 0.1OV.
Note 5: TRI-STATE may be attained using UE or '
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 " ceramic capacitor be used on
every device between Voc and GND.
Note 7: The outputs must be restricted to Vcc + 1.0V to avoid latch-up and device damage.
Note tk 1 TTL Gate: IOL --- 1.6 mA, IOH = -400 "
CL: 100 pF includes fixture capacitance.
Note 9: Vpp may be connected to Vcc except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
V90£ZOWN
NMC27C64
Programming Characteristics (Notesl,2,3 a. 4)
Symbol Parameter Conditions Mln Typ Max Units
us Address Setup Time 2 p5
tOES OT Setup Time 2 p.3
toss CE Setup Time 2 us
tDS Data Setup Time 2 ps
tvps Vpp Setup Time 2 ps
ttttts VCC Setup Time 2 ps
tAH Address Hold Time 0 p5
tDH Data Hold Time 2 us
tty: Output Enable to Output Float Delay tTE" = " 0 130 ns
tpw Program Pulse Width 0.45 0.5 0.55 ms
tog Data Valid from UE CE = " 150 ns
lpp Vpp Supply Current During 1‘; Ihr. 30 m A
Programming Pulse P M = Vit.
'00 V00 Supply Current 10 mA
TA Temperature Ambient 20 25 30 ''C
VCC Power Supply Voltage 5.75 6.0 6.25
Vpp Programming Supply Voltage 12.2 13.0 13.3 V
tFR Input Rise, Fall Time 5 ns
" Input Low Voltage 0.0 0.45 V
" Input High Voltage 2.4 4.0 " V
th Input Timing Reference Voltage 0.8 1.5 2.0 V
tour Output Timing Reference Voltage 0.8 1.5 2.0 V
Programming Waveforms (Note 3)
ADDRESSES
D ATA BhTA IN STABLE
PROGRAM
ADDRESS N
PROGRAM
VERIFY ------
F-----
5...._;:1:f:
nuuourvum
f-----
Note 1: National's standard product warranty applies to devices programmed to specifications described herein.
Note 2: Vcc must be applied simultaneously or betore Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vcc,
TL/D/8634-6
Not. 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
suppiy to prevent any overshoot trom exceeding this 14V maximum specification. At least a 0.1 WF capacitor is required across Vpp, Va: to GND to suppress
spurious voltage transients which may damage the device.
Not. 4: Programming and program verify are tested with the interactive Program Algorithm, at typical power supply voltages and timings.
V9OLZOWN
NMC27C64
Interactive Programming Algorithm Flow Chart
ADDR = FIRST LOCATION
( X = t)
---ri PROGRAM ONE .5 ms PULSE )
INCREMENT X
INCREMENT ADDR LAST ADDR ,
Vcc-- VPP= 5.0V t 5 x
DEVICE .
FAILED
DEVICE
FAILED
DEVICE PASSED
TL/D/8634-5
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C64 are listed in
Table l. It should be noted that all inputs for the six modes
are at TTL levels. The power supplies required are Vcc and
Vpp. The Vpp power supply must be at 13.0V during the
three programming modes, and must be at 5V in the other
three modes. The Vcc power supply must be at 6V during
the three programming modes, and at 5V in the other three
modes.
Read Mode
The NMC27C64 has two control functions, both of which
must be logically active in order to obtain data at the out-
puts. Chip Enable ttXt) is the power control and should be
used for device selection. Output Enable (CE) is the output
control and should be used to gate data to the output pins,
independent of device selection. The programming pin
(m) should be at Ihr, except during programming. Assum-
ing that addresses are stable, address access time (tAcc) is
equal to the delay from tTE to output (tog). Data is available
at the outputs tog after the falling edge of UTE, assuming
that CE has been low and addresses have been stable for
at least tAcc-tOE.
The sense amps are clocked for fast access time. Vcc
should therefore be maintained at operating voltage during
read and verify. If Vcc temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to insure proper output data.
Standby Mode
The NMC27C64 has a standby mode which reduces the
active power dissipation by 99%, from 55 mW to 0.55 mW.
The NMC27C64 is placed in the standby mode by applying
a CMOS high signal to the tX input. When in standby mode,
the outputs are in a high impedance state, independent of
the UE input.
Output OR-Tylng
Because NMC27C64s are usually used in larger memory
arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-Iine control function allows for:
To most efficiently use these two control lines, it is recom-
mended that tre (pin 20) be decoded and used as the pri-
mary device selecting function, while tri; (pin 22) be made a
common connection to all devices in the array and connect-
ed to the READ line from the system control bus. This as-
sures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
NMC27C64.
Initially, all bits of the NMC27C64 are in the "I Ft state. Data
is introduced by selectively programming "Os" into the de-
sired bit locations. Although only "Os" will be programmed,
both "Is" and "Os" can be presented in the data word. A
"o" cannot be changed to a "I" once the bit has been
programmed.
The NMC27C64 is in the programming mode when the Vpp
power supply is at 13.0V and TX? is at VIH. It is required that
at least a 0.1 pF capacitor be placed across Vpp, Vcc to
ground to suppress spurious voltage transients which may
damage the device. The data to be programmed is applied 8
bits in parallel to the data output pins. The levels required
for the address and data inputs are TTL.
For programming, E should be kept TTL low at all times
while Vpp is kept at 13.0V.
When the address and data are stable, an active low, TTL
program pulse is applied to the PGN input. A program pulse
must be applied at each address location to be pro-
grammed. The NMC27C64 is designed to be programmed
with interactive programming, where each address is pro-
grammed with a series of 0.5 ms pulses until it verifies (up to
a maximum of 20 pulses or 10 ms). The NMC27C64 must
not be programmed with a DC signal applied to the PtTM
input.
Programming multiple NMC27C64s in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirements. Like inputs of the paralleled
NMC27C64s may be connected together when they are
programmed with the same data. A low level TTL pulse ap-
a) the lowest possible memory power dissipation, and plied to the PGM input programs the paralleled
. . NMC27C64s.
b) complete assurance that output bus contention will not
occur.
TABLE I. Mode Selection
Pins E E PGM Vpp Vcc Outputs
Mode (20) (22) (27) (1) (28) (11-13, 15- 19)
Read " " VIH 5V 5V DOUT
Standby VIH Don't Care Don't Care SV SV Hi-Z
Output Disable Don't Care VIH " 5V 5V Hi-Z
Program . VI. VIH 13V 6V DIN
Program Verify " " Ihr, 13V 6V DOUT
Program Inhibit V.H Don't Care Don't Care 13V 6V Hi-Z
VQOLZOWN
NMC27C64
Functional Description (Continued)
Program Inhibit
Programming multiple NMC27C64s in parallel with different
data is also easily accomplished. Except for a; all like in-
puts (including tX and PGM) of the parallel NMC27C64
may be common. A TTL low level program pulse applied to
an NM027CS4's PGM input with CE at " and Vpp at 13.0V
will program that NMC27C64. A TTL high level UE input
inhibits the other NMC27C64s from being programmed.
Program Verity
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 13.0V. Vpp must be at
Vcc, except during programming and program verity.
MANUFACTURER'S IDENTIFICATION CODE
The NMC27C64 has a manufacturer's identification code to
aid in programming. The code, shown in Table II, is two
bytes wide and is stored in a ROM configuration on the chip.
It identities the manufacturer and the device type. The code
for the NMC27C64 is "8FC2", where "8F" designates that it
is made by National Semiconductor, and "CK' designates a
64k part.
The code is accessed by applying 12V 1 0.5V to address
pin A9. Addresses A1-A8. A10-A12, E, and tX are held
at VIL. Address A0 is held at " for the manufacturer's
code, and at VIH for the device code. The code is read out
on the 8 data pins. Proper code access is only guaranteed
at 25''C , tPC,
The primary purpose of the manufacturer's identification
code is automatic programming control. When the device is
inserted in a EPROM programmer socket, the programmer
reads the code and then automatically calls up the specific
programming algorithm for the part. This automatic pro-
gramming control is only possible with programmers which
have the capability of reading the code.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C64 are such that
erasure begins to occur when exposed to light with wave-
lengths shorter than approximately 4000 Angstroms (A). it
should be noted that sunlight and certain types of fluores-
cent lamps have wavelengths in the 3000h-4000h range.
After programming, opaque labels should be placed over
the NMC27C64's window to prevent unintentional erasure.
Covering the window will also prevent temporary functional
failure due to the generation of photo currents.
The recommended erasure procedure for the NMC27C64 is
exposure to short wave ultraviolet light which has a wave-
length of 2537 Angstroms A. The integrated dose (i.e., UV
intensity x exposure time) for erasure should be a minimum
of 15W-sec/cm2.
The NMC27C64 should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum NMC27C64 erasure time for various
light intensities.
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (It
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when in.
complete erasure was the problem.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, loo.
has three segments that are of interest to the system de-
signer-the standby current level. the active current level,
and the transient current peaks that are produced by volt-
age transitions on input pins. The magnitude of these tran-
sient current peaks is dependent on the output capacitance
loading of the device. The associated Vcc transientvoltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 pF ceramic
capacitor be used on every device between VCC and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 p.F bulk electrolytic
capacitor should be used between Vcc and GND for each
eight devices, The bulk capacitor should be located near
where the power supply is connected to the array. The pur-
pose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
TABLE II. Manufacturer’s Identification Code
Plns A0 o, th, Os O4 Os 02 o, 00 Hex
(10) (19) (18) (17) (16) (15) (13) (12) (11) Data
Manufacturer Code " 1 0 0 0 1 1 1 1 BF
Device Code VIH 1 1 0 0 0 0 1 0 C2
TABLE III. Minimum NMC27C64 Erasure Time
Light Intensity Erasure Time
(Mittro-Watts/crn2) (Minutes)
15,000 20
10,000 25
5,000 50
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
NMC27C64QE150 - product/nmc27c64qe150?HQS=T|-nuII-null-dscataIog-df-pf-null-wwe
NMC27C64Q300 - product/nch7c64q300?HQS=T|-null-null-dscatalog-df—pf—nuII-wwe
NMC27C64Q250 - product/nch7064q250?HQS=T|-null-null-dscatalog—df—pf—nuII-wwe
NMC27C64Q200 - product/nmc27c64q200?HQS=T|-null-null-dscatalog-df—pf—nuII-wwe
NMC27C64Q150 - product/nm027064q150?HQS=T|-null-null-dscatalog-df-pf—nuII-wwe
NMC27C64QM250 - productlnch7c64qm250?HQS=T|—null-null-dscatalog-df—pf—nuII-wwe
NMC27C64QM200 - product/nmc27c64qm200?HQS=T|—nul|—null-dscatalog-df—pf—nuII-wwe
NMC27C64QE200 - product/nmc27c64qe200?HQS=T|—nuII-nulI-dscatalog-df—pf-nuII-wwe
