NMC27C64N200 ,200 ns, Vcc=5V+/-10%, 65,536-bit (8k x 8) one time programmable CMOS PROMBlock Diagram
DATA OUTPUTS th-th
Vcc - ----"-----,
6ND _
VPP o---
trs OUTPUT ENABLE
F ..
NMC27C64N250 ,250 ns, Vcc=5V+/-10%, 65,536-bit (8k x 8) one time programmable CMOS PROMElectrical Characteristics
Symbol 4 Parameter Conditions Min Typ Max Units
ILI Input Load Current ..
NMC27C64Q150 , 64KBit (8192 x 8) CMOS EPROM [Life-time buy]General Description
The NMC27C64 is a high-speed 64k UV erasable and elec-
trically reprogramma ..
NMC27C64Q-150 , 64KBit (8192 x 8) CMOS EPROM [Life-time buy]NMC27C64
National
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NMC27C64 65,536-Bit (8k x 8)
NMC27C64Q-150. , 64KBit (8192 x 8) CMOS EPROM [Life-time buy]applications where fast turnaround, pattern experimentationcombines high performance and high densi ..
NMC27C64Q200 ,200 ns, Vcc=5V+/-10%, 65,536-bit (8k x 8) UV erasable CMOS PROMGeneral Description
The NMC27C64 is a high-speed 64k UV erasable and elec-
trically reprogramma ..
OM4068H ,LCD driver for low multiplex ratesGENERAL DESCRIPTION1⁄3The OM4068 is a low-power CMOS LCD driver, designed• 32 segment driversto dri ..
OM4068H/2 ,OM4068; LCD driver for low multiplex rates
OM4085T/F1 ,OM4085; Universal LCD driver for low multiplex rates
OM5193H ,Disk drive spindle and VCM with servo controller
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NMC27C64N200-NMC27C64N250
200 ns, Vcc=5V+/-10%, 65,536-bit (8k x 8) one time programmable CMOS PROM
I National
[ Semiconductor
NMC27C64N 65,536-Bit (8k x 8)
One-Time Programmable CMOS PROM
General Description
The NMC27C64N is a high-speed 64k one-time programma-
bie CMOS PROM. It is ideally suited for high volume produc-
tion applications where low cost, fast turnaround, and low
power consumption are important factors and reprogram-
ming is not required.
The NMC27C64N is designed to operate with a single + 5V
power supply with :10% tolerance. The NMC27C64N is
packaged in a 28-pin duaI-in-iine plastic molded package
without a transparent lid. This part is ideally suited for high
volume production applications where cost is an important
factor and programming only needs to be done once. Also
the plastic molded package works well in auto insertion
equipment used in automated assembly lines.
This device is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low pow-
er consumption and excellent reliability.
Features
I: Clocked sense amps for fast access time down to
150 ns, CMOS technology
ll Low CMOS power consumption
- Active Power: 55 mW max
- Standby Power: 0.55 mW max
I: Pin compatible with all 64k EPROMs
II Fast and reliable programming
" Static operation-no clocks required
I: TTL, CMOS compatible inputs/outputs
n TRl-STATE® output
a Optimum PROM for total CMOS systems
I: Manufacture’s identification code for automatic pro-
gramming control
Block Diagram
om ouwms th-th
he o-.
GND cy--
VP? o--.
OUTPUT ENABLE
AND CHIP
ENABLE Lotlte
OUTPUT
9.151%
DECOD ER
AO-AI?
ADDRESS
INPUTS
DECODER
BUFFERS
Y SAYING
65,538-8IT
CELL MATRIX
r-------"-----
Pln Names
A0-A12 Addresses
Ct? Chip Enable
ff Output Enable
OO-O; Outputs
PGM Program
NC No Connect
TL/D/9686-1
NVQOLZOWN
NMC27C64N
Connection Diagram
27C5t227C25627C128 27C3 27014 NMC27cs4N 27c16 27C32 27C128 27C256 270512
27512 27256 27128 2732 2716 Dual-ln-Line Package 2716 2732 27128 27256 27512
A15 Vpp Vpp VPP - 1 28 - ht: Vcc V00 V00
A12 A12 A12 Ae-? 27-..nN PG_M A14 A14
A7 A7 A7 A7 A7 A7 - a 25 - "c vcc Vcc A13 A13 A13
A6 A6 A6 A6 A6 M - 4 25 - M A8 A8 A8 A8 A8
A5 A5 A5 A5 A5 " A 5 " - " A9 A9 A9 A9 A9
A4 A4 A4 A4 A4 M -- a " - m Vpp A11 A11 A11 A11
A3 A3 A3 A3 A3 " - 1 22 - lit ttE tTE/i/rv, t7E" Ur; ttE/Ver,
A2 A2 A2 A2 A2 M - a 21 - " A10 A10 A10 A10 A10
A1 A1 A1 A1 A1 M - 9 20 - tTE tTE/Nm E CE TTi/PGM' CE
A0 A0 A0 A0 A0 M - 10 19 - th O7 O7 o, 07 O7
00 th 00 00 00 00 - ll 18 - h Os ths ths 05 os
th o, 01 Ch th 01- 12 17 - h Os Os Os Os Os
02 02 O2 02 02 Oe - 13 18 - 04 O4 O4 O4 O4 04
GND GND GND GND GND Mo- " 15 - o, th 03 th 03 Os
TL/D/9686-2
Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C64N pins.
Order Number NMC27C64N
See NS Package Number N288
Commerclal Temp Range (O‘C to + 70°C)
Vcc = 5V i10%
Parameter/Order Number Access Tlme ins)
NMC27C64N150 150
NMC27CS4N200 200
NMC27C64N250 250
(For Non Ctttttttterttlat Temp. Range Parts, Can Factory)
Absolute Maximum Ratings (Note1)
If Mllltary/Aerospace trpecitled devices are required,
please contact the National Semiconductor Sales
Otfltte/Dltttrlttutttrtt for avallablllty and ttpeelflttatluna.
Temperature Under Bias - 10'C to + 80°C
Storage Temperature - 65"C to + 150''C
All Input Voltages except A9 with
Respect to Ground (Note 10)
All Output Voltages with
Respect to Ground (Note 10)
Vpp Supply Voltage and A9
+ 6.5V to -0.6V
Vcc+1.0Vto GND-0.6V
Vcc Supply Voltage with
Respect to Ground + 7.0V to -0.6V
Power Dissipation 1.0W
Lead Temperature (Soldering, 10 sec.) 300°C
ESD Rating
(Mil Spec 8830, Method 3015.2) 2000V
Operating Conditions (Note 7)
Temperature Range
Vcc Power Supply
ty'C to + 70''C
with Respect to Ground NMC27C64N150, 200, 250 + 5V i10%
During Programming + 14.0V to -0.6V
READ OPERATION
DC Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
ILI Input Load Current VIN = VCC or GND 10 WA
ico Output Leakage Current VOUT = Vcc or GND,CE = Ihr., 10 pA
ICC1 Vcc Current (Active) CE = Vic, f = 5 MHz 6 20 m A
(Note 9) TTL Inputs Inputs = ViH or VI, NC = 0 mA
lccg Vcc Current (Active) CE = GND,f = 5 MHz 3 10 m A
(Note 9) CMOS Inputs Inputs = Vcc or GND, l/O = 0 mA
ICCSB1 Vcc Current (Standby) E = VIH o. 1 1 m A
TTL Inputs
‘CCSBZ /gifiTC,ttftandtv) CE V00 0.5 100 .. P A
lpp Vpp Load Current Vpp = V00 10 [J.A
" Input Low Voltage - 0.1 0.8 V
VIH Input High Voltage 2.0 Vcc + 1 V
V0L1 Output Low Voltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage lor, = -400 mA 2.4 V
V0L2 Output Low Voltage kx = 0 FA 0.1 V
VOH2 Output High Voltage 'OH = 0 pA VCC - 0.1 V
AC Electrical Characteristics
NMC27C64N
Symbol Parameter Conditions 150 200 250 Units
Min Max Min Max Min Max
tACC Address to Output Delay 'pi-rc--- W = " 150 200 250 ns
PGM = VIH
tCE CEto Output Delay W = VIL, PTN = VIH 150 200 250 ns
tog tTi? to Output Delay tTE = V.L. p-tFM- = ng 60 60 70 ns
top UE- High to Output Float CT? = lhc, PWM = le 60 60 o 60 ns
to; CE High to Output Float CT: = v.L, Ft-Wt = " o 60 60 60 ns
tOH Output Hold from Addresses, E = tfE = W.
Cl? or CE Whichever FG-M = VIH 0 0 0 ns
Occurred First
NVQOLZOWN
NMC27C64N
Capacitance TA = +25°C,f = 1 MHz (Note 2)
Symbol Parameter Condltlons Typ Max Unlts
ths Input Capacitance VIN = 0V 5 10 pF
COUT Output Capacitance VOUT = 0V 8 10 pF
AC Test Conditions
Output Load 1 TTL Gate and Timing Measurement Reference Level
CL == 100 pF (Note 8) Inputs 0.8V and 2V
Input Rise and Fall Times s5 ns Outputs 0.8V and 2V
Input Pulse Levels 0.45V to 2.4V
AC Waveforms (Notes 6, 7 & 9)
ADDRESSES 2" ADDRESSES VALID ::
a 35v y,- y
K 3Y3v l y, y
" to: - tor -
Hi 2 (NOTE 3) I (NOVELS) HI 2
2V l- ' "" -
OUTPUT W t VALID OUTPUT ', ""
(NOTE 3) --to"
rr . TL/D/9686-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: UE may be delayed up to hot: - toe after the falling edge of CE without impacting tACC.
Note 4: The tm: and tCF compare level is determined as follows:
High to TRI-STATE, the measured Vom (DC) - 0.10V;
Low to TRI-STATE, the measured Vor: (DC) + 0.10V.
Note 5: TFll-STATE may be attained using E or CE.
Note 6: The power switching characteristics of EPROMs require cavatul device decoupling. It is recommended that at least a 0.1 pF ceramic capacitor be used on
every device between Vcc and GND.
Note r.. The outputs must be restricted to Vcc + 1.0V to avoid latch-up and device damage.
Note & 1 TTL Gate: 'OL = 1.6 mA, km = -400 "
CL: 100 pF includes fixture capacitance.
Note th Vpp may be connected to Vcc except during programming.
Note 10: Inputs and outputs can undershoot to -0.2V for 20 ns Max.
Programming Characteristics (Notes1, 2, 3 & 4)
Symbol Parameter Conditlons Min Typ Max Units
tAs Address Setup Time 2 us
tOES UE Setup Time 2 ps
tCES CE Setup Time 2 [.LS
tos Data Setup Time 2 [us
tvps Vpp Setup Time 2 us
Ms Vcc Setup Time 2 us
tAH Address Hold Time 0 ps
tDH Data Hold Time 2 p5
top Output Enable to Output Float Delay TX = VI. O 130 ns
tpw Program Pulse Width 0.45 0.5 0.55 ms
tog Data Valid from tTE rx == " 150 ns
|pp Vpp Supply Current During EEL-rt " 30 m A
Programming Pulse PG = "
ICC V00 Supply Current 10 mA
TA Temperature Ambient 20 25 30 (
Vcc Power Supply Voltage 5.75 6.0 6.25 V
Vpp Programming Supply Voltage 12.2 13.0 13.3
tFR Input Rise, Fall Time 5 ns
" Input Low Voltage 0.0 0.45 V
vm Input High Voltage 2.4 4.0 ' 'v
th Input Timing Reference Voltage 0.8 1.5 2.0 V
tOUT Output Timing Reference Voltage 0.8 1.5 2.0 V
Note 1: Nationttl's standard product warranty applies to devices programmed to specifications described herein.
Note 2: Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vcc.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least 0.1 pF capacitor is required across MPP, Vcc to GND to suppress
spurious voltage transients which may damages the device.
Note 4: Programming and program verify are tested with the Interactive Program Algorithm, at typical power supply voltages and timings.
NVQOLZOWN
NMC27C64N
Programming Waveforms (Note a)
PROGRAM VERWY
PROGRAM
ADDRESSES 2Y ADDRESS u
DATA "NIP"
VPP tvps
DATA OUT VAUD
TL/D/9686-4
Interactive Programming Algorithm Flow Chart
ADDR = F IRST LOCATION
CE-ECC)
---ri PROGRAM ONE 0.5 ms PULSE )
INGREDIENT X
INCREMENT ADDR LAST ADDR?
Vcc=VPP=5.0V 15%
DEVICE
FAILED
DEVICE
FAILED
DEVICE PASSED
TL/D/9686-5
NVQOLZOWN
NMC27C64N
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C64N are listed in
Table I. It should be noted that all iniputs for the six modes
are at TTL levels. The power supplies required are Vcc and
Vpp. The Vpp power supply must be at 13.0V during the
three programming modes, and must be at 5V in the other
three modes. The VCC power supply must be at 6V during
the three programming modes, and at 5V in the other three
modes.
Read Mode
The NMC27C64N has two control functions, both of which
must be logically active in order to obtain data at the out-
puts. Chip Enable (O_E) is the power control and should be
used for device selection. Output Enable it5t?) is the output
control and should be used to gate data to the output pins,
independent of device selection. The programming pin
(m) should be at " except during programming. Assum-
ing that addresses are stable, address access time (tAcc) is
equal to the delay from ttE to output (tog). Data is available
at the outputs tOE after the falling edge of GE. assuming
that CE has been low and addresses have been stable for
at least tACC-tOE.
The sense amps are clocked for fast access time. Vcc
should therefore be maintained at operating voltage during
read and verify. If Vcc temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to insure proper output data.
Standby Mode
The NMC27C64N has a standby mode which reduces the
active power dissipation by 99%, from 55 mW to 0.55 mW.
The NMC27C64N is placed in the standby mode by applying
a CMOS high signal to the ttE input. When in standby mode,
the outputs are in a high impedance state, independent of
the TX input.
Output OR-Tylng
Because NMC27C64Ns are usually used in larger memory
arrays, National has provided a 2-iine control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recom-
mended that CE (pin 20) be decoded and used as the pri-
mary device selecting function, while W (pin 22) be made a
common connection to all devices in the array and connect-
ed to the READ line from the system control bus. This as-
sures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
NMC27C64N.
Initially, all bits of the NMC27C64N are in the "I" state.
Data is introduced by selectively programming "Os" into the
desired bit locations. Although only "Os" will be pro-
grammed, both "Is" and “Os" can be presented in the data
word. A "0" cannot be changed to a "I" once the bit has
been programmed. Due to package constraints programma-
bility of the device is only tested in water form.
The NMC27C64N is in the programming mode when the
Vpp power supply is at 13.0V and Ut? is at VIH. it is required
that at least a 0.1 WF capacitor be placed across Vpp, VCC
to ground to suppress spurious voltage transients which
may damage the device. The data to be programmed is
applied 8 bits in parallel to the data outputs pins. The levels
required for the address and data inputs are TTL.
For programming, tT should be kept TTL low at all times
while Vpp is kept at 13.0V.
When the address and data are stable, an active low, TTL
program pulse is applied to the PGM input. A program pulse
must be applied at each address location to be pro-
grammed. The NMC27C64N is designed to be programmed
with interactive programming, where each address is pro-
grammed with a series of 0.5 ms pulses until it verifies (up to
a maximum of 20 pulses or 10 ms). The NMC27C64N must
not be programmed with a DC signal applied to the PGM
input.
Programming multiple NMC27C64Ns in parallel with the
same data can be easily accomplished due to the simplicity
of the programming requirements. Like inputs of the paral-
leled NMC27C64Ns may be connected together when they
are programmed with the same data, A low level TTL pulse
applied to the pt-jd input programs the paralleled
NMC27C64Ns.
The NMC27C64N is packaged in a plastic molded package
which does not have a transparent lid. Therefore the memo-
ry cannot be erased. This means that after a user has pro-
grammed a memory cell to a "O'' it cannot be changed back
to a "I ".
If an application requires erasing and reprogramming, the
NMC27C64Q UV erasable PROM in a windowed package
should be used.
TABLE I. Mode Select
Pins E "trti PGM Vpp Vcc Outputs
Mode [ (20) (22) (27) (1) (28) (11-13, 15-19)
Read " " 5V 5V DOUT
Standby Don't Don't .
Ihr, Care Care 5V 5V Hi-Z
Program VIL VIH 13.0V 6V DIN
Program Verify " " 13.0V 6V DOUT
Program Inhibit Don't Don't .
VIH Care Care 13.0V 6V Hi-Z
Output Disable Don't '
Care VIH 5V 5V Hi-Z
Functional Description (Continued)
Program Inhibit
Programming multiple NMC27C64Ns in parallel with differ..
ent data is also easily accomplished. Except for CT? all like
inputs (including trr: and W) of the parallel NMC27C64N
may be common. A TTL low level program pulse applied to
an NMC27C64Ns PG-M input with E at W. and Vpp at
13.0V will program that NMC27C64N. A TTL high level CE
input inhibits the other NMC27C64Ns from being pro-
grammed.
Program Verity
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 13.0V. Vpp must be at
Vcc, except during programming and program verity.
MANUFACTURER'S INDENTIFICATION CODE
The NMC27C64N has a manufacturer’s identification code
to aid in programming. The code, shown in Table II, is two
bytes wide and is stored in a ROM configuration on the chip.
It identifies the manufacturer and the device type. The code
for the NMC27C64N is "8FC2", where "8F" designates that
it is made by National Semiconductor, and "C2" designates
a 64k part.
The code is accessed by applying 12V :0.5V to address
pin A9. Addresses A1-A8, A10-A12, CE and 5? are held
at VIL. Address A0 is held at " for the manufacturer‘s
code, and at " for the device code. The code is read out
on the 8 data pins. Proper code access is only guaranteed
at 25°C i5°C.
The primary purpose of the manufacturer’s identification
code is automatic programming control. When the device is
inserted in an EPROM programmer socket, the programmer
reads the code and then automatically calls up the specific
programming algorithm for the part. This automatic pro-
gramming control is only possible with programmers which
have the capability of reading the code.
SYSTEM CONSIDERATION
The power switching characteristics of this device require
careful decoupling. The supply current, ICC, has three seg-
ments that are of interest to the system designer-the
standby current level, the active current level, and the tran-
sient current peaks that are produced by voltage transitions
on input pins. The magnitude of these transient current
peaks is dependent on the output capacitance loading of
the device. The associated VCC transient voltage peaks can
be suppressed by properly selected decoupling capacitors.
It is recommended that at least a 0.1 pF ceramic capacitor
be used on every device between Vcc and GND. This
should be a high frequency capacitor of low inherent induc-
tance. In addition, at least a 4.7 pF bulk electrolytic capaci-
tor should be used between Vcc and GND for each eight
devices. The bulk capacitor should be located near where
the power supply is connected to the array. The purpose of
the bulk capacitor is to overcome the voltage drop caused
by the inductive effects of the PC board traces.
TABLE II. Manufacturer's Identification Code
Pins A0 Or Os ths 04 O3 02 l 00 Hex
(10) (19) (18) (17) (16) (15) (13) (12) (11) Data
Manufacturer Code " 1 0 0 0 1 1 1 1 BF
Device Code V.H l 1 0 0 0 0 1 0 Ge
NVQOLZOWN
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
NMC27C64N250 - product/nm027064n250?HQS=T|-nu|I-null-dscataIog-df-pf-null-wwe
NMC27C64N150 - product/nm027064n150?HQS=T|-nu|I-nulI-dscatalog-df—pf-nuII-wwe
NMC27C64N200 - product/nm027c64n200?HQS=T|-nu|I-nulI-dscatalog-df—pf-nuII—wwe
