NMC27C512AQ-170 ,170 ns, Vcc=5V+/-10%, 524,288-bit (64k x 8) UV erasable CMOS PROMElectrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
IL. Input Load Current F ..
NMC27C512AQ20 ,200 ns, Vcc=5V+/-5%, 524,288-bit (64k x 8) UV erasable CMOS PROMGeneral Description
The NMC27C512A is a high-speed 512k UV erasable and
electrically reprogramm ..
NMC27C512AQ200 ,200 ns, Vcc=5V+/-10%, 524,288-bit (64k x 8) UV erasable CMOS PROMNational
Semiconductor
NMC27C512A
PRELIMINARY
524,288-Bit (64k x 8) UV Erasable CMOS PROM ..
NMC27C512AQ200 ,200 ns, Vcc=5V+/-10%, 524,288-bit (64k x 8) UV erasable CMOS PROMapplications where fast turnaround, pattern experiments
tion and low power consumption are importa ..
NMC27C512AQ-200 ,200 ns, Vcc=5V+/-10%, 524,288-bit (64k x 8) UV erasable CMOS PROMFeatures
I Ciocked sense amps for fast access time down to
150 ns
I Low CMOS power consumpti ..
NMC27C512AQ250 ,250 ns, Vcc=5V+/-10%, 524,288-bit (64k x 8) UV erasable CMOS PROMBlock Diagram
ltltthWtNT80r4tt
Rrt>--
'tmo--.
Wro--
Pln Names
Chip Enable
Output E ..
OM4068H ,LCD driver for low multiplex ratesGENERAL DESCRIPTION1⁄3The OM4068 is a low-power CMOS LCD driver, designed• 32 segment driversto dri ..
OM4068H/2 ,OM4068; LCD driver for low multiplex rates
OM4085T/F1 ,OM4085; Universal LCD driver for low multiplex rates
OM5193H ,Disk drive spindle and VCM with servo controller
OM5202FBB ,ROMless 8-bit microcontroller
OM5604 ,Multimedia radio tuner
NMC27C512AQ15-NMC27C512AQ150-NMC27C512AQ-150-NMC27C512AQ170-NMC27C512AQ-170-NMC27C512AQ20-NMC27C512AQ200-NMC27C512AQ-200-NMC27C512AQ250-NMC27C512AQE-200-NMC27C512AQE250-NMC27C512AQE-250
150 ns, Vcc=5V+/-5%, 524,288-bit (64k x 8) UV erasable CMOS PROM
I National
Semiconductor
NMC27C512A
PRELIMINARY
524,288-Bit (64k x 8) UV Erasable CMOS PROM
General Description
The NMC27C512A is a high-speed 512k UV erasable and
electrically reprogrammabie CMOS EPROM, ideally suited
for applications where fast turnaround, pattern experimenta-
tion and low power consumption are important require-
ments.
The NMC27C512A is designed to operate with a single
+5V power supply with 15% or 110% tolerance. The
CMOS design allows the part to operate over extended and
military temperature ranges.
The NMC27C512A is packaged in a 28-pin dual in-line pack-
age with transparent lid. The transparent lid allows the user
to expose the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written electrically into the device
by following the programming procedure.
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low pow-
er consumption and excellent reliability.
Features
I: Clocked sense amps for fast access time down to
150 ns
II Low CMOS power consumption
- Active Power: 110 mW max
- Standby Power: 0.55 mW max
rt Optimum EPROM for total CMOS system
Extended temperature range (NMC27C512At2E),
-40'C to 85°C, and military temperature range
(NMC27C512AQM), -55''C to 125°C, available
Pin compatible with NMOS 512k EPROM
Fast and reliable programming-too p5 typical/byte
Static operation-no clocks required
TTL, CMOS compatible inputs/outputs
THLSTATEG output
Manufacturer's identification code for automatic pro-
gramming control.
I: High current CMOS level output drivers
Block Diagram ,
am more,
Re _ e----"-----,
w o--.
VZLSOLZOWN
TL/D/iF-t
Pin Names
A0-A15 Addresses
Ut? Chip Enable
t5E/vrv, Output Enable/ Pro-
gramming Voltage
00-07 Outputs
FtTh7 Program lil
NM0270512A
Connection Diagram
270256 270128 27064 27032 27016 NMC27C512At2 27016 27032 27064 270126 270256
27256 27128 2764 2732 2716 Dual-ln-Line Package 2716 2732 2764 27128 27256
VPP l/pp VPP m - , n - ttt 1(p_p, yt_oto Vcc
A12 A12 A12 Mt-t n '-M4 PGM PGM A14
A7 A7 A7 A7 A7 " - ' N - m Vcc Vcc NC A13 A13
A6 A6 A6 A6 A6 a - 1 " - " A8 A8 A8 A8 M
A5 A5 A5 A5 A5 " - s " g " A9 A9 A9 A9 A9
A4 A4 A4 A4 A4 u-u I n -m Vpp A11 A11 A11 A11
A3 M A3 A3 M " - , tt - um, t:7E" TE/i/pr, E 'tit E
A2 A2 A2 A2 A2 "- ' 21 - m A10 A10 A10 A10 A10
A1 A1 A1 A1 A1 u- , n p-ts C_E/Vpp CE CE tTit Crt
A0 A0 A0 A0 A0 a - to tt - h o, O7 O7 O7 O7
00 Oo 00 00 00 h- n u - o. Os th 06 th, 06
O1 O1 o, O1 01 the tt It --h Os Os Os Os Os
O2 02 02 O2 O2 o, -..1 " u - tk 04 04 O4 O4 04
GND GND GND GND GND "o- u 15 h 03 03 03 Os 03
TLm/9181-2
Order Part Number NMC27CS12AQ
See NS Package Number J28AO
Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C512A pins.
Commercial Temp Range (0°C to + 70°C) Commercial Temp Range (tr'C to + 70'C)
Vcc = 5V i5% Vcc = 5V $1079
Parameter/Order Number Access Time (ns) Parameter/Order Number Access Tlme (ns)
NMC27C512AO15 150 NMC27C512At2150 150
NMC27C512AtM7 170 NMC27C512AQ170 170
NMC27C512A020 200 NMCZ7C512A0200 "200
NMC27C512At225 250 NMC27C512At2250 250
Extended Temp Range i-- 40''C to + 85°C) Mllltary Temp Range (- 55'C to + 125°C)
Vcc = 5V i10% Vcc = 5V 110%
Parameter/Order Number Access Time (ns) Parameter/Order Number Access Time (ns)
NMC27C512AaE150 150 NMC27C512AQM150 150
NMC270512AQE170 170 NMC27C512AaM170 170
NMC27C512AQE200 200 NMC27C512AQM200 200
NMC27C512AOE250 250 NMC270512AQM250 250
NOTE: For plastic DIP and surface mount PLCC package requirements please refer to NMC27C5t2AN data sheet.
All Input Voltages except A9 & tTE/Vee
COMMERCIAL TEMPERATURE RANGE
Absolute Maximum Ratings (Note1)
Temperature Under Bias
Storage Temperature
with Respect to Ground (Note 9)
Vcc Supply Voltage with
Respect to Ground
ESD Rating
(Mil. Std. 8830, Method 3015.2)
- 10°C to + 8ty'C
- 65''C to + 15ty'C
+ 6.5V to -0.6V
+ 7.0V to -0.6V
Wivpp Supply Voltage & A9
with Respect to Ground
Power Dissipation
Lead Temperature (Soldering, 10 sec.)
+ 14.0V to --0,6V
Operating Conditions (Note 6)
Temperature Range
Vcc Power Supply
WC to + 70"C
All Output Voltages with NMC27C512AQ15, 17, 20, 25 5V d: 5%
Respect to Ground (Note 9) Vcc + 1.0V to GND--0.6V NMC27C512AQ150, 170, 200, 250 5V i 10%
READ OPERATION
DC Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
ILI Input Load Current VIN = Vcc or GND 0.01 1 pA
ILO Output Leakage Current VOUT = Vcc or GND, 3 = ViH 0.01 1 WA
Ipp Vpp Load Current TX/vm, = VCC or GND 10 pA
ICC1 Vcc Current (Active) CE = VIL, f == 5 MHz 15 30 mA
TTL Inputs Inputs = " or VIL, I/O = 0 mA
ICCZ VCC Current (Active) 'C.E = GND,t = 5 MHZ 10 20 mA
CMOS Inputs Inputs = VCC or GND, I/O = 0 mA
lccsm #(L; fe2nt (Standby) CE VIH 0.1 1 r m A
ICCSBQ ticgi1r,rCltts(standby) GE Vcc 0.5 1 00 H A
" Input Low Voltage -0.2 0.8 V
VIH Input High Voltage 2.0 vcc + 1 V
VOL1 Output Low Voltage IOL = 2.1 mA 0.40 V
VOH1 Output High Voltage IOH = -2.5 mA 3.5 V
V0L2 Output Low Voltage '01. = 10 piA 0.1 V
VOH2 Output High Voltage lor, = - 10 11A Vcc - 0.1 V
AC Electrical Characteristics
NMC27C5t2A
Symbol Parameter Conditions 015, 0150 017, 0170 020, 0200 025, 0250 Units
Min Max Min Max Min Max Min Max
tACC Address to Output Delay CE =- W = " 150 170 200 250 ns
105 CE to Output Delay OT: = " 150 170 200 250 ns
tOE UEto Output Delay t7 = " 60 75 75 100 ns
tDF W High to Output Float E = " 50 55 55 0 60 ns
tCF CE High to Output Float 6T; = " 50 55 55 60 ns
10H 1httputAtold from Addresses, CE = CE = "
CE or OE, Whichever 0 0 0 0 ns
Occurred First
VZLSOLZOWN
NMC27C512A
MILITARY AND EXTENDED TEMPERATURE RANGE
Absolute Maximum Ratings (Note1)
If Mllltary/Aerospace specltlod devlces are required, Lead Temperature (Soldering, 10 sec.) 300°C
please contact the National Sttntittttrtduetttr Sales Vcc Supply Voltage with
Otfltte/DlMrlbutttrs for avallablllty and ttttttttImation-s. Respect to Ground + 7.0V to -0.6V
Temperature Under Bias Operating Temp, Range ESD Rating
Storage Temperature -65'C to + 150'C (Mil, Std. 883C, Method 3015.2) 2000V
All Input Voltages except A9 & E/Vpp . . .
with Respect to Ground (Note 9) + 6.5V to -0.6V Operating Conditions (Note 6)
All Output Voltages with Temperature Range
Respect to Ground (Note 9) Vcc+ 1.0V to GND-0.6V NMC27C256BQE150, 170, 200, 250 -40''C to + 85'C
GEIVPP Supply Voltage & A9 NMC27C256Bt2M150, 170, 200, 250 -55'C to +125'C
with Respect to Ground +14.0V10 -0.6V Vcc Power Supply + 5V t 10%
Power Dissipation 1 .OW
READ OPERATION
DC Electrical Characteristics
Symbol Parameter Condltlons Mln Typ Max Unlts
ILI Input Load Current VIN = Vcc or GND 10 FA
ILO Output Leakage Current VOUT = Vcc or GND, E = VIH 10 FA
|cc1 Vcc Current (Active) E = lhL,t = 5 MHz 15 30 m A
TTL Inputs Inputs = VIH or VIL, I/O == 0 mA
I092 VCC Current (Active) E = GND,t = 5 MHz 10 20 m A
CMOS Inputs Inputs = Vcc orGND, I/O == 0 mA
|CCSB1 ¥TCE 51:35: (Standby) E " 0.1 l . m A
lccssz 1tiguc,'lts(standby) E V00 0.5 100 M A
Im, Vpp Load Current E/Vpp = Vcc or GND 10 WA
VIL Input Low Voltage -0.2 0.8 V
VIH Input High Voltage 2.0 Vcc + 1 V
VOL1 Output Low Voltage IOL = 2.1 mA 0.4 V
VOH1 Output High Voltage 10H = -1.6 mA 3.5 V
V0L2 Output Low Voltage lot. = 10 PA 0.1 V
VOH2 Output High Voltage IOH = -10 WA Vcc - 0.1 V
AC Electrical Characteristics
NMC27C512A
Symbol Parameter Condltlons 0E150, QM150 QE170, GM170 OE200, QM200 0E250, OM250 Units
Mln Max Mln Max Min Max Min Max
tAcc Address to Output Delay tTi? = E = " 150 170 200 250 ns
ICE co, Output Delay E = " 150 170 200 250 ns
tog Etc Output Delay E = " 60 75 75 100 ns
to; E High to Output Float E =T " 0 50 0 55 0 55 0 60 ns
to; CE High to Output Float ESE = " o 50 o 55 o 55 o 60 ns
tor, Output Hold from Addresses, E = E = "
CE or E, Whichever 0 0 0 0 ns
Occurred First
Capacitance TA = +25''C,f = 1 MHz (Note 2)
Symbol Parameter Conditions Typ Max Units
C|N1 Input Capacitance " = 0V
except UE/ver, 6 12 pF
COUT OutputCapacitance VOUT = 0V 9 12 pF
CiN2 tr/ve, Input " = ov 20 25 pF
Capacitance
AC Test Conditions
Output Load 1 TTL Gate and Timing Measurement Reference Level
CL = 100 pF (Note 8) Inputs th8V and 2V
Input Rise and Fall Times $5 ns Outputs 0.8V and 2V
Input Pulse Levels 0.45V to 2.4V
AC Waveforms (Notes6, 7)
ADDRESSES B)t ADDRESSES VALID :: y
- LT P"""-""
CE 0.8V n y
F“ -ctse
tc: (Roma)
- 2.0V
OE/be o.sv lt g; y
tor: tar -
btw Hi l 4 (NOTES) - " *(Nom's) H' I
. I' --a3 h t"
OUTPUT T.ii7" VALID OUTPUT y, m,
ttot: ---- __. - ,-
(NOTE 3) thl
TL/D/9181-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated In the operational sections of this stratification is not implied, Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note & UE may be delayed up to tACC - 105 after the falling edge otCE without impacting tAcc-
Note 4: The top and Icy: compare level is determined as follows:
High to TRl-STATE, the measured VOH1 (DC) _ 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) + 0.1OV.
Note s: TRl-STATE may be attained using (f or CE.
Note 8: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 WF ceramic capacitor be used on
every device between Vcc and GND.
Note r.. The outputs must be restricted to Vcc + 1.0V to avoid Iatch-up and device damage.
Note 8: 1 TTL Gate: IOL = 1.6 mA, ky., = -400 WA.
CL: 100 pF includes fixture capacitance.
Note 9: Inputs and outputs can undarshoot to -2.OV for 20 ns Max.
VZl-SOAZOWN
NMC27C512A
Programming Characteristics (Notes1,2, 3 and 4)
Symbol Parameter Conditions Min Typ Max Units
Us Address Setup Time 1 ps
toes at- Setup Time 1 us
tos Data Setup Time 1 ps
tvcs Vcc Setup Time 1 us
tAH Address Hold Time 0 ps
tDH Data Hold Time 1 us
tet Chip Enable to Output Float Delay tX = " 0 60 ns
tpw Program Pulse Width 95 100 105 p.s
tOEH o-E Hold Time 1 us
by Data Valid from C-E E = " 250 ns
tpm- tTi? Pt? Rise Tiny 50 ns
During Programming
tvn Vpp Recovery Time 1 Its
Ipp Vpp Supply Current During E = " 30 m A
Programming Pulse OE = Vpp
lcc Vcc Supply Current 10 mA
Tn Temperature Ambient 20 25 30 "C
Vcc Power Supply Voltage 6 6.25 6.5
Vpp Programming Supply Voltage 12.5 12.75 13
TFR Input Rise, Fall Time 5 ns
" Input Low Voltage 0 0.45 V
VIH Input High Voltage 2.4 4 V
th Input Timing Reference Voltage 0.8 1 .5 V
tour Output Timing Reference Voltage 0.8 1.5 2 V
Note 1: National‘s standard product warranty applies to devices programmed to specifications described herein.
Note 2: VCC must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage appred to Vpp or VCC-
Nole 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least 0.1 HF capacitor is required across Vcc to GND to suppress spurious
voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the fast Program Algorithm, at typical powet supply voltages and timings.
Programming Waveforms
ADDRESSES
" 0.8V
12.75v
PROGRAM
ADDRESS N
PROGRAM
DHAMVALD MI
Vcc 6.25Y
TL/D/9181-5
Fast Programming Algorithm Flow Chart (Note 4)
ADDR = FIRST LOCATION
PROGRAM ONE 100 p3 PULSE
WITH vPP = 12.75v
INCREMENT X
DEVICE - .
FAILED
INCREMENT ADDR
LAST ADDR ?
VERIFY DEVICE
ALL BYTES FAILED
DEVICE PASSED
TL/ D/9181 - 7
FIGURE 1
VZLSOLZOWN
NMCZ7CS12A
Interactive Programming Algorithm Flow Chart (Note 4)
ADOR = FIRST LOCATION
|NCREMENT ADDR
PROGRAM ONE 0.5 ms PULSE
wrm b, = 12.5v
LAST ADDR ,
vcc=s.ov:sz
DEVICE, -
FABLED
FAILED
DEVICE PASSED
FIGURE 2
TL/Dm181-6
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C512A are listed
in Table l. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for UE/Vpp during
programming. In the program mode the O-E/vm, input is
pulsed from a TTL low level to 12.75V.
Read Mode
The NMC27C512A has two control functions, both of which
must be logically active in order to obtain data at the out-
puts. ChipEnable (E) is the power control and should be
used for device selection. Output Enable (ttE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tAcc) is equal to the delay
from CE to output (ice). Data is available at the outputs after
the falling edge of UE, assuming that E has been low and
addresses have been stable for at least tAcc-toe.
The sense amps are clocked for fast access time. Vcc
should therefore be maintained at operating voltage during
read and verify. If Vcc temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to insure proper output data.
Standby Mode
The NMC27C512A has a standby mode which reduces the
active power dissipation by over 99%, from 110 mW to
0.55 mW. The NMC27C512A is placed in the standby mode
by applying a CMOS high signal to the E input When in
standby mode, the outputs are in a high impedance state,
independent of the tTE input.
Output OR-Tylng
Because NM0270512A are usually used in larger memory
arrays, National has provided a 2-Iine control function that
accommodates this use of multiple memory connections.
The 2Aine control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recom-
mended that Ttfi (pin 20) be decoded and used as the pri-
mary device selecting function, while ttE/Vps, (pin 22) be
made a common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in their
low power standby modes and that the output pins are ac-
tive only when data is desired from a particular memory de-
Programming
CAUTION: Exceeding 14V on pin 22 (5E/Vpp) will damage
the NMC27C512A.
Initially, and after each erasure, all bits of the NMC27C512A
are in the "I '' state. Data is introduced by selectively pro-
gramming "Os" into the desired bit locations. Although only
"Os" will be programmed, both "Is" and "Os" can be pre-
sented in the data word. The only way to change a "ty' to a
"I" is by ultraviolet light erasure.
The NMC27C512A is in the programming mode when the
trE/vrn, is at 12.75V. It is required that at least a 0.1 pF
capacitor be placed across Vcc and ground to suppress
spurious voltage transients which may damage the device.
The data to be programmed is applied 8 bits in parallel to
the data output pins. The levels required for the address
and data inputs are TTL.
When the address and data are stable, an active low, TTL
program pulse is applied to the C-E input. A program pulse
must be applied at each address location to be pro-
grammed.
The NMC27C512A is programmed with the Fast Program-
ming Algorithm shown in Figure 1. Each Address is pro-
grammed with a series of 100 ps pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
Program with a single 100 p5 pulse.
The NMC27C512A_must not be programmed with a DC sig-
nal applied to the CE input.
Programming multiple NMC27C512AS in parallel with the
same data can be easily acccomplished due to the simplici-
ty of the programming requirements. Like inputs of the par-
alleled NMC27C512A may be connected together when
they are programmed with the same data. A low level TTL
pulse applied to the WE input programs the paralleled
NMC27C512A.
Note: Some programmer manufacturers due to equipment limitation may
offer interactive program Algorithm (Shown in Figure 2).
TABLE I. Mode Selection
Pins C-E tNi/vm, Vcc Outputs
Mode (20) (22) (28) (11-13,15-19)
Read VI L Vit. 5.0V DOUT
Standby ViH Don't Care 5.0V Hi-Z
Program VI. 12.75V 6.25V DIN
Program Verify " " 6.25V DOUT
Program Inhibit VIH 12.75V 6.25V Hi-Z
Output Disable Don't Care " 5.0V Hi-Z
VZLSOLZOWN
NMC27CS12A
Functional Description (Continued)
Program lnhlblt
Programming multiple NMC27C512A in parallel with differ..
ent data is also easily accomplished. Except trE all like in-
puts (including E) of the parallel NMC27C512A may be
common. A TTL low level program pulse applied to an
NMC27C512A's E input with c7iUVros, at 12.75V will pro-
gram that NMC27C512A. A TTL high level CE input inhibits
the other NMC27C512A from being programmed.
Program Verity
A verity should be performed on the programmed bits to
determine whether they were correctly programmed. The
verity is accomplished with Oi/rn, and E at VIL. data
should be verified le after the falling edge of '
Manufacturer’s Identification Code
The NMC27C512A has a manufacturer’s identification code
to aid in programming. The code, shown in Table ii, is two
bytes wide and is stored in a ROM configuration on the chip.
It identifies the manufacturer and the device type. The code
for the NMC27C512A is, "8F 85", where "8F" designates
that it is made by National Semiconductor, and "85'' desig-
nates a 512k part.
The code is accessed by applying 12V fc0.5V to address
pin A9. Addresses AI-M, A10-A15, E, and E are held
at VIL. Address A0 is held at Ihr. for the manufacturer‘s
code, and at VIH for the device code. The code is read on
the 8 data pins. Proper code access is only guaranteed at
25°C d: 5°C.
The primary purpose of the manufacturer’s identification
code is automatic programming control. When the device is
inserted in an EPROM programmer socket, the programmer
reads the code and then automatically calls up the specific
programming algorithm for the part. This automatic pro-
gramming control is only possible with programmers which
have the capability of reading the code.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27CS12A are such
that erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000h-4000h
range.
After programming opaque labels should be placed over the
NMC27C512A's window to prevent unintentional erasure.
Covering the window will also prevent temporary functional
failure due to the generation of photo currents.
The recommended erasure procedure for the
NMC27C512A is exposure to short wave ultraviolet light
which has a wavelength of 2537 Angstroms (A). The inte-
grated dose (i.e., UV intensity x exposure time) for eraSure
should be a minimum of 15W-sec/cm2.
The NMC27C512A should be placed within 1 inch of the
lamp tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table Ill
shows the minimum NMC27C512A erasure time for various
light intensities.
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (lf
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed, or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when im
complete erasure was the problem.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, ICC,
has three segments that are of interest to the system de-
signer-the standby current level, the active current level,
and the transient current peaks that are produced by volt.
age transitions on input pins. The magnitude of these tran-
sient current peaks is dependent on the output capacitance
loading of the device. The associated Vcc transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 “F ceramic
capacitor be used on every device between Vcc and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 " bulk electrolytic
capacitor should be used between Vcc and GND for each
eight devices. The bulk, capacitor should be located near
where the power supply is connected to the array. The pur-
pose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
TABLE II. Manutacturer's Identification Code
Plns A0 07 Os Os 04 03 02 o, 00 Hex
(10) (19) (18) (17) (16) (15) (13) (12) (11) Data
Manufacturer Code " 1 0 0 0 1 1 1 1 BF
Device Code VIH 1 0 0 0 0 1 0 1 85
TABLE III. Minimum NMC27C512A Erasure Time
Light intensity
(Micro-Watts/emo
Erasure Time
(Minutes)
15,000
10,000
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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NMC27C512AQ170 - product/nm027c512aq170?HQS=TI—nu|I—nu|I-dscatalog-df-pf-nulI-wwe
NMC27C512AQ15 - product/nmc27c512aq15?HQS=T|—nuII-nulI-dscatalog-df—pf-nuII-wwe
NMC27C512AQE250 - product/nmc27c512aqe250?HQS=TI-nulI-nuIl-dscataIog-df-pf-null-wwe
NMC27C512AQM150 - product/nmc27c51Zaqm150?HQS=T|-nulI-null-dscatalog-df—pf—nuII-wwe
NMC27C512AQ25 - product/nm027c512aq25?HQS=T|-nulI-nulI-dscatalog-df—pf—nuII-wwe
NMC27C512AQ250 - product/nmc27c512aq250?HQS=TI—nu|I—nu|I-dscatalog-df-pf-nulI-wwe
NMC27C512AQE150 - product/nm027c512aqe150?HQS=TI-nulI-nuIl-dscataIog-df-pf-null-wwe
NMC27C512AQE170 - product/nm027051Zaqe170?HQS=Tl-null-nuIl-dscataIog-df-pf-null-wwe
NMC27C512AQE200 - productlnmc27c512aq9200?HQS=T|—null-nuIl-dscataIog-df-pf-null-wwe
NMC27C512AQ20 - product/nmc27c512aq20?HQS=T|—nuII-nulI-dscatalog—df—pf-nuII-wwe
NMC27C512AQM170 - product/nm0270512aqm170?HQS=T|-nulI-null-dscatalog-df—pf—nulI-wwe
NMC27C512AQM200 - product/nm027c512aqm200?HQS=TI-nulI-null-dscatalog-df—pf—nuII-wwe
NMC27C512AQM250 - product/nmc27c512aqm250?HQS=TI-nulI-null-dscatalog-df—pf—nuII-wwe
NMC27C512AQ200 - product/nm027c512aq200?HQS=TI—nu|I—nu|I—dscatalog-df-pf-nulI-wwe
