NMC27C256Q-200 ,200 ns, Vcc=5V+/-10%, 262,144-bit (32k x 8) UV erasable CMOS PROMNational
Semiconductor
NMC27C256
262,144-Bit (32k x 8) UV Erasable CMOS PROM
NMC27C256Q25 ,250 ns, Vcc=5V+/-5%, 262,144-bit (32k x 8) UV erasable CMOS PROMBlock Diagram _
am OUTPUTS lk-th
lltt; H
mm o--
1tre o---
0mm! EMILE
mo cm! Pin Nam ..
NMC27C256Q-25 ,250 ns, Vcc=5V+/-5%, 262,144-bit (32k x 8) UV erasable CMOS PROMapplications where fast turnaround, pattern experiments l Low CMOS power consumption
9SZOLZOWN
..
NMC27C256Q-25 ,250 ns, Vcc=5V+/-5%, 262,144-bit (32k x 8) UV erasable CMOS PROMElectrical Characteristics
Symbol Parameter Conditions Min Typ Max Unlts
IL, Input Load Current V ..
NMC27C256Q250 ,250 ns, Vcc=5V+/-10%, 262,144-bit (32k x 8) UV erasable CMOS PROMNational
Semiconductor
NMC27C256
262,144-Bit (32k x 8) UV Erasable CMOS PROM
NMC27C256Q-250 ,250 ns, Vcc=5V+/-10%, 262,144-bit (32k x 8) UV erasable CMOS PROMBlock Diagram _
am OUTPUTS lk-th
lltt; H
mm o--
1tre o---
0mm! EMILE
mo cm! Pin Nam ..
OES021ZC-A ,One - Ultra-Dense 40W converter
OM4068H ,LCD driver for low multiplex ratesGENERAL DESCRIPTION1⁄3The OM4068 is a low-power CMOS LCD driver, designed• 32 segment driversto dri ..
OM4068H/2 ,OM4068; LCD driver for low multiplex rates
OM4085T/F1 ,OM4085; Universal LCD driver for low multiplex rates
OM5193H ,Disk drive spindle and VCM with servo controller
OM5202FBB ,ROMless 8-bit microcontroller
NMC27C256Q17-NMC27C256Q-17-NMC27C256Q20-NMC27C256Q-20-NMC27C256Q200-NMC27C256Q-200-NMC27C256Q25-NMC27C256Q-25-NMC27C256Q250-NMC27C256Q-250-NMC27C256Q300-NMC27C256QE200-NMC27C256QE250-NMC27C256QE-250
170 ns, Vcc=5V+/-5%, 262,144-bit (32k x 8) UV erasable CMOS PROM
I National
_ Semiconductor
NMC27C256
262,144-Bit (32k x 8) UV Erasable CMOS PROM
General Description
The NMC27C256 is a high-speed 256k UV erasable and
electrically reprogrammable CMOS EPROM, ideally suited
for applications where fast turnaround, pattern experiments
tion and low power consumption are important require-
ments.
The NMCZ70256 is designed to operate with a single + 5V
power supply with 15% or i10% tolerance. The CMOS
design allows the part to operate over extended and military
temperature ranges.
The NMC27C256 is packaged in a 28-pin dual in-line pack-
age with transparent lid. The transparent lid allows the user
to expose the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written electrically into the device
by following the programming procedure.
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low pow-
er consumption and excellent reliability.
Features
a Clocked sense amps for fast access time down to
170 ns
II Low CMOS power consumption
- Active power: 55 mW max
- Standby power: 0.55 mW max
I! Performance compatible to NSCBOOTM CMOS micro-
processor
II Single 5V power supply
I: Extended temperature range (NMC27C256t2E),
-40'C to +85''C, and military temperature range
(NMC27C256QM), -55"C to +125''C, available
a Pin compatible with NMOS 256k EPROMs
a Fast and reliable programming (0.5 ms for most bytes)
u Static operation-no clocks required
I: TTL, CMOS compatible inputs/outputs
u TRI-STATE' output
I: Optimum EPROM for total CMOS systems
Block Diagram
om OUTPUTS h-th
1ao--+
e-----"----
eno o--
Itrr _
6E OUTPUT mm
mo cmr oumn
M mm Loeic sums:
ADDRESS
INPUTS
' GATING
262.1444"
CELL MATRIX
Pin Names
A0-A14 Addresses
E Chip Enable
fl Output Enable
00-07 Outputs
PTm Program
NC No Connect
TL/D/7512-1
SSZOLZOWN
NMCZ7C256
Connection Diagram
270512 270128 27064 27032 27016 NMC27C256t2 27016 27032 27064 270128 270512
27512 27128 2764 2732 2716 DuaI-ln-Llne Package 2716 2732 2764 27128 27512
A15 VPP VPP m, - 1 " - Rt; Vcc V00 V00
A12 A12 A12 Alt--? 17--htt 'RTM PGM A14
A7 A7 A7 A7 A7 n - a 28 - m Vcc Vcc NC A13 A13
A6 A6 A6 A6 A6 " - 4 25 - " A8 A8 A8 A8 A8
A5 A5 A5 A5 A5 A5 - 5 " - " A9 A9 A9 A9 A9
A4 A4 A4 A4 A4 " - s " - m Vpp A11 A11 A11 A11
A3 A3 A3 M M A: - , " - m E O-E/vm, O_E o-E TE/Vps,
A2 A2 A2 A2 A2 " - a 21 - A10 A10 A10 A10 A10 A10
A1 A1 A1 A1 A1 A1-- ' 20 - mm tTE/PGM E CE Ul? Ut?
A0 A0 A0 M A0 M - lil 19 - th th O7 Or Or th
00 th 00 00 00 h _ ll 18 - h 06 ths Os 06 06
o, O1 o, O1 o, th --. 12 17 - tts Os Os Os 05 Os
02 02 02 O2 O2 h ".- 13 16 - o. 04 O4 O4 04 04
GND GND GND GND GND tlilo-. 14 15 - h 03 03 03 Os Os
TL/D/7512-2
Nola: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NM0270256 pins.
Order Number NMC27C256t2
See NS Package Number J28AQ
Commercial Temp Range (0°C to + 70°C) Commercial Temp Range (tt'C to '+"70°C)
V00 = 5V i5% Vcc = SV t10%
Parameter/Order Number Access Tlme Parameter/Order Number Access Tlme
NMC27C256t217 170 NMC27C2560200 200
NMC27C256tM0 200 NMC27C256O250 250
NMC27C256t225 250 NMC27C256tM00 300
Extended Temp Range (-40°c to + 85°C) Mllltary Temp Range (- 55''C to + 125''C)
Vcc --- 5V 110% Vcc = 5V £1096
Parameter/Order Number Access Time Parameter/Order Number Access Time
NMC27C256QE200 200 NM027C2560M250 250
NMC27C256CE250 250 NM027C2560M350 350
NOTE: For plastic DIP and surface mount PLCC package requirements please refer to NMC27C256BN data sheet.
COMMERCIAL TEMPERATURE RANGE
Absolute Maximum Ratings (Note1)
Temperature Under Bias -lty'C to +80''C
Storage Temperature -65''C to + 15ty'C
All Input Voltages with
Respect to Ground (Note 10)
All Output Voltages with
Respect to Ground (Note 10)
Vpp Supply Voltage with Respect
to Ground During Programming
vcc+ 1.0V to GND-0.6V
+14.0Vto - 0.6V
Power Dissipation 1.0W
Lead Temperature (Soldering, 10 sec.) 300°C
Vcc Supply Voltage with
Respect to Ground + 7.0V to - 0.6V
+ 6.5V to -th6V
Temperature Range
Vcc Power Supply
Operating Conditions (Note?)
0°C to + 70'C
NMC27C256Q17, 20, 25 5V t5%
NMC2702560200, 250, 300 5V , 10%
READ OPERATION
DC Electrical Characteristics
Symbol Parameter Conditions Mln Typ Max Units
IL, Input Load Current VIN = VCC or GND 10 WA
'Lo Output Leakage Current VouT = Vcc or GND, CE == w, 10 HA
lcc1 Vcc Current (Active) C-E = VlL,f = 5 MHz 6 20 m A
(Note 9) TTL Inputs Inputs = Ihr, orV1., I/O = 0 mA
'002 Vcc Current (Active) tTE = GND,f = 5 MHz 3 10 mA
(Note 9) CMOS Inputs Inputs = Vcc or GND, l/O = 0 mA
lccsBl I,),'? gigzznt (Standby) CE VIH 0.1 1 _ m A
lccsgg 2Cgrr,r,tts(standby) CE Vcc 0.5 1 00 M A
Ipp Vpp Load Current Vpp = Vcc 10 pA
" Input Low Voltage -0.1 0.8 V
VIH Input High Voltage 2.0 VCC + 1 V
VOL1 Output Low Voltage IOL = 2.1 mA 0.45 V
V0H1 Output High Voltage lor, = -400 p.A 2.4 V
VOL2 Output Low Voltage 10L = 0 ”A 0.1 V
VOH2 Output High Voltage IOH = 0 p Vcc - 0.1 V
AC Electrical Characteristics
NM0276256
Symbol Parameter Conditions 017 020, 0200 Q25, 0250 0300 Units
Min Max Mln Max Min Max Min Max
tACC Addressto Output Delay UE = tE = " 170 200 250 300 ns
ICE CE to Output Delay GE = " 170 200 250 300 ns
tog UE'to Output Delay tTE = " 75 75 100 120 ns
kr CT? High to Output Float 5? = " 60 0 60 0 60 105 ns
tap CE High to Output Float E = VI. 60 0 60 0 60 105 ns
tOH Output Hold from Addresses, CE = UE = Ihr.
C? or Ut?, Whichever 0 O 0 0 ns
Occurred First
SSZOLZOWN
NMC27C256
MILITARY AND EXTENDED TEMPERATURE RANGE
Absolute Maximum Ratings (Note1)
If Military/Aerospace specified devlces are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias Operating Temp Range
Storage Temperature -65'C to + 15ty'C
All Input Voltages with
Respect to Ground (Note 10)
All Output Voltages with
Respect to Ground (Note 10)
Vpp Supply Voltage with
Respect to Ground
During Programming
+ 6.5V to - 0.6V
Vcc+ 1.0V to GND-0.6V
+ 14.0V to -0.6V
Power Dissipation
Lead Temperature (Soldering, 10 sec.)
Vcc Supply Voltage with
Respect to Ground
30ty'C
+ 7.0V to -0.6V
Operating Conditions (Note 7)
Temperature Range
N MC27C2560E200, 250
NMC27C256OM250, M350
-4ty'C to + 85''C
-55''C to + 125°C
Vcc Power Supply 5V i 10%
READ OPERATION
DC Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
ILI Input Load Current VIN = Vcc or GND 10 p.A
ILO Output Leakage Current VOUT = Vcc or GND, tTE = " 10 pA
lcc1 VCC Current (Active) tTE = Vct = 5 MHz 6 20 m A
(Note 9) TTL Inputs Inputs = VIH or VIL, I/O = 0 mA
Iccg VCC Current (Active) E = GND,f = 5 MHz 3 10 m A
(Note 9) CMOS Inputs Inputs = Vcc or GND, l/O = 0 mA
|CCSB1 Vcc Current (Standby) tett" = VIH 0.1 i m A
TTL Inputs
Iccsgg tSiuC'ftftandby) GE V00 0.5 100 H A
Ipp Vpp Load Current Vpp = V00 10 “A
VIL Input Low Voltage -0.1 0.8 V
" Input High Voltage 2.0 Vcc + 1 V
VOL1 Output Low Voltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage IOH = -400 pa/k 2.4 V
VOL? Output Low Voltage IOH = 0 p.A 0.1 V
VOH2 Output High Voltage IOH = 0 p.A Vcc - 0.1 V
AC Electrical Characteristics
NMC27C256t2
Symbol Parameter Conditions E200 E250 M350 Units
Min Max Min Max Min Max
tACC Address to Output Delay UE == UE = " 200 250 350 ns
tog Eto Output Delay E = VI. 200 250 350 ns
tog E to Output Delay E = VIL 75 100 120 ns
to}: E High to Output Float E = " 0 60 0 60 0 105 ns
tOH Output Hold from Addresses, E = E = "
E or E Whichever 0 0 0 ns
Occurred First
to; E High to Output Float E = " 0 60 0 60 0 105 ns
Capacitance TA = +25°c.t = 1 MHz (Note 2)
Symbol Parameter Conditions Typ Max Units
Cm InputCapacitance VIN = 0V 6 12 pF
Cour Output Capacitance VOUT = ov 9 12 pF
AC Test Conditions
Output Load 1 TTL Gate and
Timing Measurement Reference Level
CL == 100 pF (Note 8) Inputs 0.8V and 2V
Input Rise and Fall Times s5 ns Outputs 0.8V and 2V
Input Pulse Levels 0.45V to 2.4V
AC Waveforms (Notes 6, 7 a 9)
ADDRESSES 2.0V ADDRESSES VALID n y
- '"""'
2.ov N,
CE O.8Y y, /t, F4
‘c: (noms4.5)
. '.ov -T
OE (21.1w ff y
,1 tos - - lor -
2 av Hi 2 (NOTE 3) I (NtrTES4,S Hi z
. - I \ l"
OUTPUT m- VALID OUTPUT or', ",,,,
- tace - _
(NOTE 3) -tor,
TL/D/7512-3
Note tt Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation ot the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: UE may be delayed up to tAct; - toe after the falling edge of CE without impacting tAcc.
Note 4: The tog: and top compare level is determined as toIlows:
High to TRl-STATE. the measured Vom (DC) - 0.10V;
Low to TRl-STATE, the measured Vat, (DC) + 0AOV,
Nob 5: TRl-STATE may be attained using UE or CE.
Note tk The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 pF ceramic capacitor be used on
every device between Vcc and GND.
Note r.. The outputs must be restricted to V0; + 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: IOL = 1.6 mA, [OH = -400 WA.
Cu: 100 pF includes fixture capacitance.
Note 9: Vpp may be connected to V00 except during programming.
Note Ith Inputs and outputs can undershoot to -2.0V tor 20 ns Max.
QSZOLZOWN
NMC27C256
Programming Characteristics (Notes1,2,3 & 4)
Symbol Parameter Condltlons Mln Typ Max Units
tAS Address Setup Time 2 p.s
1053 W Setup Time 2 us
typs Vpp Setup Time 2 ps
tvcs Vcc Setup Time 2 us
103 Data Setup Time 2 ps
tAH Address Hold Time 0 us
tDH Data Hold Time 2 P3
tor Output Enable to Output Float Delay t5tt = VIL 0 130 ns
tpw Program Pulse Width 0.5 0.5 10 ms
tog Data Valid from -0t? CE = Iht. 150 ns
lpp Vpp Supply Current During CE = " 30 m A
Programming Pulse m = "
ICC Vcc Supply Current 10 mA
TA Temperature Ambient 20 25 30 (
VCC Power Supply Voltage 5.75 6.0 6.25 V
Vpp Programming Supply Voltage 12.2 13.0 13.3 V
trn Input Rise, Fall Time 5 ns
" Input Low Voltage 0.0 0.45 V
VIH Input High Voltage 2.4 4.0 V
th Input Timing Reference Voltage 0.8 1.5 2.0, ' V
tour Output Timing Reference Voltage 0.8 1.5 2.0 V
Note 1: Natitmal's standard produc1warranty applies only to devices programmed to specifications described herein.
Note 2: Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or V00.
Note 3: The maximum absolute allowable voltages which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 pF capacitor is required actoss Vpp. vet: to GND to suppress
spurious voltage transients which may damage the device.
Note 4: Programming and program verify are tested with the Interactive Program Algorithm, a1 typical power supply voltages and timings.
Programming Waveforms (Note a)
ADDR ESSES
DATA " um I: sun:
TL/D/7512-4
Interactive Programming Algorithm Flow Chart
ADDR = FIRST LOCATION
l X = 0 )
--H PROGRAM ONE .5 ms PULSE )
INGREDIENT It
INCREMENT ADDR LAST ADDR ?
vcc= v”: 5.0V , s T,
DEVICE
FAILED
DEVICE
FAILED
VERIFY
AU. BYTES
DEVICE PASSED
FIGURE 1
TL/D/7512-5
QSZOLZOWN
NMC27C256
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C256 are listed in
Table I. It should be noted that all inputs for the six modes
are at TTL levels. The power supplies required are Vcc and
Vpp. The Vpp power supply must be at 13.0V during the
three programming modes, and must be at 5V in the other
three modes. The VCC power supply must be at 6V during
the three programming modes, and at 5V in the other three
modes.
Read Mode
The NMC27C256 has two control functions, both of which
must be logically active in order to obtain data at the out-
puts. Chip Enable (trE) is the power control and should be
used for device selection. Output Enable (tTE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tAcc) is equal to the delay
from CE to output (tog). Data is available at the outputs tog
after the falling edge of E, assuming that a has been low
and addresses have been stable for at least tACC - tog.
The sense amps are clocked for fast access time. Vcc
should therefore be maintained at operating voltage during
read and verify. If Vcc temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to ensure proper output data.
Standby Mode
The NMC27C256 has a standby mode which reduces the
active power dissipation by 99%, from 55 mW to 0.55 mW.
The NMC27C256 is placetli_ntho standby mode by applying
a CMOS high signal to the CE input. When in standby mode,
the o_utputs are in a high impedance state, independent of
the OE input.
Output OFl-Tylng
Because NMC27C256s are usually used in larger memory
arrays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recom-
mended that CTE (pin 20) be decoded and used as the pri-
mary device selecting function, while o-E (pin 22) be made a
common connection to all devices in the array and connect-
ed to the READ line from the system control bus. This as-
sures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on pin 1 (Vpp) will damage the
NMC27C256,
Initially, and after each erasure, all bits of the NMC27C256
are in the "I" state. Data is introduced by selectively pro-
gramming "Os" into the desired bit locations. Although only
"Os" will be programmed, both "ls" and "Os" can be pre-
sented in the data word. The only way to change a "o" to a
"I" is by ultraviolet light erasure.
The NMC27C256 is in the programming mode when the Vpp
power supply is at 13.0V and Ut? is at VIH. It is required that
at least a 0.1 pLF capacitor be placed across Vpp, VCC to
ground to suppress spurious voltage transients which may
damage the device. The data to be programmed is applied 8
bits in parallel to the data output pins. The levels required
for the address and data inputs are TTL.
When the address and data are stable, an active low TTL
program pulse is applied to the CE/PRN input. A program
pulse must be applied at each address location to be pro-
grammed. Any location may be programmed at any time--
either individually, sequentially, or at random. The
NMC27C256 is designed to be programmed with interactive
programming, where each address is programmed with a
series of 0.5 ms pulses until it verifies (up to a maximum of
20 pulses or 10 ms). The NMC27C256 must not be pro-
grammed with a DC signal applied to the trE/PtiM input.
Programming multiple NMC27C256s in parallel with the
same data can be easily accomplished due to the simplicity
of the programming requirements. Like inputs of the paral-
leled NMC27C256s may be connected together when they
are programmed with the same data. A low level TTL pulse
applied to the CE/PtiM input programs the paralleled
NMC27C256s.
TABLE l. Mode Selection
Pins cam E Vpp Vcc Outputs
Mode (20) (22) it) (28) (11-13, 15-19)
Read " " 5V 5V DOUT
Standby ViH Don't Care SV SV Hi-Z
Program " VIH 13.0V 6V DIN
Program Verify VIH " 13.0V 6V DOUT
Program Inhibit VIH VIH 13.0V 6V Hi-Z
Output Disable Don't Care VIH 5V 5V Hi-Z
Functional Description (Continued)
Program lnhlblt
Programming multiple NMC27C256s in parallel with differ-
ent data is also easily accomplished. Except for Tht" all like
inputs (including W) of the parallel NMC27C256s may be
common. A TTL low level program pulse applied to an
NMC27C256's "tTi/P-tW/ input with Vpp at 13.0V will pro-
gram that NMC27C256. A TTL high level ter? input inhibits
the other NMC27C256s from being programmed.
Program Verity
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with Vpp at 13.0V. Vpp must be at
V00, except during programming and program verify.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C256 are such
that erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). it should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000A-4000A
range.
After programming, opaque labels should be placed over
the NMC27C256's window to prevent unintentional erasure.
Covering the window will also prevent temporary functional
failure due to the generation of photo currents.
The recommended erasure procedure for the NMC27C256
is exposure to short wave ultraviolet light which has a wave-
length of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity M exposure time) for erasure should be a minimum
of 15W-sec/cm2.
The NMC27C256 should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table II
shows the minimum NMC27C256 erasure time for various
light intensities.
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (lf
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when in-
complete erasure was the problem.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, ICC,
has three segments that are of interest to the system de-
signar-the standby current level, the active current level,
and the transient current peaks that are produced by volt-
age transitions on input pins. The magnitude of these tran-
sient current peaks is dependent on the output capacitance
loading of the device. The associated Vcc transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 pF ceramic
capacitor be used on every device between vet: and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 pF bulk electrolytic
capacitor should be used between Vcc and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The pur-
pose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
TABLE II. Minimum NM0270256 Erasure Tlme
Light Intensity Erasure Time
(Mlcro-Watts/cm2) (Minutes)
1 5,000 20
10,000 25
5,000 50
QSZOLZOWN
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
NMC27C256QM250 - product/nm0270256qm250?HQS=TI-nu|I-nu|I-dscataIog-df-pf-null-wwe
NMC27C256QE250 - product/nm0270256qe250?HQS=T|-nuIl-nu|I-dscatalog-df-pf-nulI-wwe
NMC27C2560E200 - product/nm027c256qe200?HQS=TI—nu|I—nu|I-dscatalog-df-pf-nulI-wwe
NMC27C256Q300 - product/nmc270256q300?HQS=TI-nu|I-null-dscataIog-df—pf-null-wwe
NMC27C256QM350 - product/nm0270256qm350?HQS=TI-nu|I-nu|I-dscataIog-df-pf-null-wwe
NMC27C256Q25 - product/nmc270256q25?HQS=T|-null-null-dscatalog-df—pf—nuII-wwe
NMC27C256Q17 - productlnch70256q17?HQS=T|-null-null-dscatalog—df—pf—nuII-wwe
NMC27C256Q20 - product/nmc27c256q20?HQS=T|-null-null-dscatalog-df—pf—nuII-wwe
NMC27C256Q200 - product/nm0270256q200?HQS=T|—nu|I-nu|I-dscataIog-df-pf-null-wwe
NMC27C256Q250 - product/nm027c256q250?HQS=TI-nu||-nu|I-dscataIog-df-pf-null-wwe
