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NMC2116N-25L |NMC2116N25LNSN/a82avai250 ns, 5 V, 1 W, 2048 x 8 static RAM


NMC2116N-25L ,250 ns, 5 V, 1 W, 2048 x 8 static RAMElectrical Characteristics (Note 1) TA = 0°C to + 70°C, VCC = 5V 110% Symbol Parameter Condition ..
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NMC2116N-25L
200 ns, 5 V, 1 W, 2048 x 8 static RAM
(rf, C;
tN-l 0/
March 1982
N 00 3 5 8 0
rybC" PRELIMINARY
S $690
NMC2rm 2046 x B btatic RAM
Max Access/Current NMC2I16-20L NMC2116-25L NM0211S-20
Access (TAVOV-ns) 200 250 200
Active Current (ICC - mA) TO 70 100
Standby Current (IS8- mA) IO 10 15
General Description Features
This 2048 x 8 static random access memory is fabricated II All inputs and outputs directly TTL compatible
using N-channel silicon-gate technology incorporating " Static operation-no clocks or refreshing required
poly-load resistors and two polysilicon layers. All internal .3 Low power-375 mW max
circuits are fully static and therefore require no clocks or n 200 ns and 250 ns max access time
refreshing ionoperation. The data is read out nondestruc- " TRI STATE' t tf b . t
tively and has the same polarity as the input data. Com. ", ou pu or us mierece
mon input/output pins are provided. " 24-pin EPROM/ROM compatibility
ll Single 5V supply
The separate chip seieet‘input allews easy memory ex- n Automatic power down
pansmn by OR-tying individual devices to a data bus and n C mm n d t i/O ins
automatically powers down the NMC2116. o C) a a p
ll Separate OE pin
Block Diagram*
Connection Diagram*
[ q-A) vcc
M o R: Dual-ln-Line Package
l, H (il/sos, l "
I ROW I MEMORY MATRIX '7- U - VCC
I DECODER o 123 HUWS 2 23
l 1 OF 128 o 128 COLUMNS Ali- - A8
: o-'. 3 MI
A6 o------)
o-' =WE(W)
. . . o-' 2us,
I/UD 6 til
T) : COLUMN I/O : A?-' -Mil
I l INPUT M 2, Lam
I I l BATA COLUMN oscupsn Ai,-', .E woman
I I CONTROL 5
l l : i/omnooii LI/nsmaai
Jf/ 3— l l i/moan'-' J?. I/osionsi
. . I I
, " ----- Ali) 1 l |/021002)l1- ilvoamnu
t -t-' cnoivssii 13 IIUJIDOJJ
JgRo- TUPVIEW
LEE c “:33?
"NM C Pin Names'
2983 Chip Select Logic Symbol'
OE (G) Output Enable
" (W) Write Enable - Au I/OO _
I/OO-l/O? (DOO-DO?) Data ln/Out - M ‘5":
AO-AIO Address Inputs - A? (001) -
VCC Power 5V -i A3 mm L___
* GND (VSS) Ground (OO?)
Truth Table - M $13 _
- - - - - - _..-.. A5
cs (S) WE (W) on ) uo Mode ii Jd') --
H X X Hi-Z Standby
- A7 nos -
L L X 1 Write 1 (mm
L L x 0 Write o - M (30066] -
L H L DOUT Read - M I/O?
' a m TE ' _
L H H HI-Z Read - A10 (El (W) (tT)" (non
"The symbols In parentheses are proposed industry standard.
TRl-STATE' IS a registered ivademark of Nation." Cnyrvcon0uctcrr Corp
1982 National Semiconductor Corp. XD/222 I Jts8-B25M32iPrrnte0 m U S A
INVH allelS 8 X 81703 QHZOINN
Absolute Maximum Ratings
Voltage at Any Pin with Respect to VSS
Storage Temperature
Temperature with Bias
DC OutputCurrent
Power Dissipation
Lead Temperature (Soldering, 10 seconds)
- 1.5V to + 7V
-65''C to + 150°C
-10''Cto + 85°C
300''C
DC Electrical Characteristics (Note 1) TA = 0''C to + 70°C, VCC = 5V t10%
Symbol Parameter Conditions :RMAEZES-Egt NMC2116.20 Units
Min Max Min Max
llL1i Input Load Current VIN = ov to VCC 10 10 “A
(All Input Pins)
moi Output Leakage & = 2.4V, 10 10 “A
Current VOUT = GND to VCC
VIL Input Low Voltage - 0.6 0.8 - 0.6 0.8 V
VIH Input High Voltage 2.0 6.0 2.0 6.0 V
VOL Output Low Voltage IOL = 4.0 mA 0.4 0.4 V
VOH Output High Voltage 10H = - 2.0 mA 2.4 2.4 V
ICC Power Supply VIN = 5.5V, TA = 0°C 70 100 mA
Current Output Open
ISB Standby Current VCC = Min to Max, c-s = VIH IO 15 mA
IPO Peak Power-On 19C = VSS to VCC Min 10 15 mA
Current cs = Lower of VCC or VIH Min
Capacitance (Note 2) TA = 25°C, f = 1.0 MHz
Symbol Parameter Conditions Min Max Units
Cl/O Input/Output Capacitance Vl/O = 0V 7 pF
CIN AddressIControl Capacitance VIN = 0V 7 pF
Note 1: These circuits require 500 us time delay after VCC reaches the specified minimum limit to insure proper operation after power on. This allows me Inter-
nally generated substrate bias to reach its functional level.
Note 2: This parameter is guaranteed by penodut testing.
AC Test Conditions
Input Pulse Levels
InputRise and FallTimes
InputTiming Level
OutputTiming Levels
Output Load
GND to 3.0V
0.8V and 2.0V
Sinking 4 mA with 100 pF (including scope and fixture)
Sourcing 2 mA with 100 pF(including scope and fixture)
Read Cycle AC Electrical Characteristics TA = 0''C to
+ 70°C, VCC = 5V t 10%
Symbol Parameter ttlttE,1,1ta2,1. NMC2116.25L Units
Alternate Standard Min Max Min Max
tnc TAVAV Read Cycle Time 200 250 ns
tAA TAVQV Address Access Time 200 250 ns
- ACS TSLQV Chip Select Access Time fz'b'o _ 250 ns(3)
tOEA TGLQV Output Enable Access Time 80 100 ns
tor2 TGLQX Output Enable to Output Active 15 15 ns
tOHZ TGHQZ Output Enable to Output TRI-STATE 60 60 ns
ICLZ TSLQX Chip Select to Output Active 20 25 ns
tCHZ TSHQZ Chip Deselect to Output TRl-STATE 0 60 0 60 ns
tOHA TAXOX Output Hold from Address Change 10 10 ns
tpU TSLIH Chip Select to Power-Up O 0 ns
tro TSHIL Chip Deselect to Power-Down 60 60 ns
Read Cycle Waveforms*
Read Cycle1(Continuous Selection t% = VIL, W5 = VIH, 6E = VIL)
(TAVAV)
ADDRESS”) (if]
10M ------tu(TNl010 1“ tom -
(TAXQX) (TAXOX)
I100T(00)
Read Cycle 2 (Chip Select Switched, WE = VIH, o-E = VIL) (Note 3)
(TAVAV)
ADDRESS (At X
1AA - lOHA -.-
(TAVOV) (TAXUX)
cs 'Rt tis,
ucs tot
(TSLOV) (TSHOZ)
"(TsLllX)
DOUT (00)
Read Cycle 3 (Output Enable Switched Fe = VIH, c-s = VIL)
(TAVAV)
ADonEss (A) _))t-(
m tang
(TAVDV) mxuxr’
_ - -\ N, 's "s, '-,
"trsirsri_', \ x tis:
<4 tou -
000T (00)
Note 3: Addresses must be valid coincident with or prior to the chip select transmon from high to low,
'The symbols m parentheses are proposed industry standard.
Write Cycle AC Electrical Characteristics TA = 0''C to + 70°C, VCC = 5V t10%
NMC2116-20
NM 1 -
Symbol Parameter NMC2116-20L C21 6 25L Units
Alternate Standard Min Max Min Max
two TAVAV Write Cycle Time 200 250 ns
tcw TSLWH Chip Select to End of Write 160 200 ns
tAS TAVSL Address Set-Up Time 0 0 ns
twp1 TWLWH1 Write Pulse Width 120 150 ns(4)
twpa TWLWH2 Write Pulse Width 170 210 ns(5)
twn TWHAX Write Recovery Time 0 0 ns
tow TDVWH Data Set-Up Time 110 135 ns
tDH TWHDX Data Hold Time 0 0 ns
twsz TWLQZ Write Enable to Output TRI-STATE 0 50 O 60 ns
tow TWHQX Output Active from End of Write 10 10 ns
Note 4: twp1 applies if a write occurs when the output is already in TRl-STATE.
Nate 5: twpz applies if a wnte occurs when the output is in low-Z state (i.e.. RMW cycle).
Write Cycle Waveforms (Notes 6 and 7)
Write Cycle 1 (t5it = VIH)
ADDRESS (A) )< -
l tcw l twn (NOTE 8)
(TSUNH) I (“NHAX) .
tsm _ \\\:\\\‘\ _ \\\\\\\\. "x \\ "e, 's, IQ? \ N x _ , "
11mm) ----e "mm”
- ' _ '; 's.
WE M, ttie, _ \\. W 7Z
l _ twr -
(WILHW)
DIN A,
Write Cycle 2 (CE = VIL)
(TAVAV)
ADDRESS (N ,
- (TSLWH)
thNnTE 8)
(TWHAX)
J “YR. ". 's N _ , \.\
kmxuxy
(TWHQX)
irsi5) I, ,,.' \
'ss, _
Note 6: The output remains TRI-STATE it the t5rs anoTirg go high simultaneously. vm? 0155 or both must be high.
Note P. iW must be high dunng all address transmons.
Note 8: IWR is measured trom the end of write cycle to the earlier of ee or " going high.
*The symbols in parentheses are proposed industvy standard.
Physical Dimensions inches(mi|limeters)
-- - - ---- i-i:Viti) - _---" ---.- il.iiim
MAX (15.2411)
l FrrshF-2lfinFrtrsLrrCFr) mm )ju E11: Ith,
0.025 _
(0.ti35)-s, .
RAD 's, 1hs_11vihyf,
(1T0ti-13.3ii)
0.510-555 / m LU mm Us! (armEm) )0) L10 El -
(th7ii2-1.397) _/
RAD Typ
- (r5M-ihii20 - cuss 0.055 10.005 (5. 000)
I t14S8ii-15.7N0 SEALANT" (1.397 0.127)+ - MAX 0020 0.070
F _ .4 1 tEiilrrsi)
95 G - 0.003410” L-T-
.0325 (0203-0505) -
l - iHi85 Mum _” 0.0500100 - - 0010 0002 35 0.125
.0535 (r524-2.50) 0‘00 0010 1"} (0.457- 0.051) 94 (irir)
(ro -t.524 Es7Ttaisa: 540 0.254) TY Gk
Ceramic Dual-In-Line Package (O)
Order Number NMC2116J-20, NMC2116J-20L
or NMC2116J415L
NS Package Number J24A
---- - irtCsii _------- --‘
Ffz5lfr21liilFCEill7hfrCrrsllrs1Fi] "
0.052 T
(1.li75)-ss, I
RAD 's _ilfC1?15,
(13.715 11,127)
PINNO.IIDENT\ l
l L1] L3] IL! Li] Ls] U] 11] L911“! L‘JTIE]
(14J3) 0.030
MIN (0.752)
ihii00- 0520 MAX - 21il 0060:0005
H 7ra7uTrraTr, 24 15, 740) lil" “-332 t" (4.0Mtlr127)
L-l-,, _ l
95 ihMil- 0.015 l 715 M
'Lee: (O. 220 0.351) m, (1.015
0015 0075- 0.015 _--- A 0.010. 0003 0125 ((1,331)
(i''LT5/,i,iirr"" (1005 0.351) i,:-:::-:-.,!.:,-::-:--, 0100 0010 _ (0457 0075) i-ii) MIN
0.301) '
(2 Mil 0.254) mm
Molded Dual-ln-Line Package (N)
Order Number NMC2116N-20, NMC2116N-20L
or NMC2116N-25L
NS Package Number N24A
This datasheet has been :
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
NMC2116J-20 - product/nmc2116j-20?HQS=T|-null-null-dscata|og-df-pf—nuII-wwe
NMC2116N-20L - product/nch116n-20]?HQS=TI-nuIl-nu|I-dscataIog-df-pf-null-wwe
NMC2116N-20 - product/nmc2116n—20?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuII-wwe
NMC2116J-25L - product/nmc2116j-25I?HQS=T|-nu|I-nulI-dscatalog-df—pf—null-wwe
NMC2116J-20L - product/nmcz116j-20I?HQS=T|-nu|I-nulI-dscatalog-df—pf-null-wwe
NMC2116N-25L - product/nch116n-25l?HQS=TI-nuIl-nu|I-dscataIog-df-pf-null-wwe
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