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NM25C04FAIN/a168avai4096-Bit CMOS Serial Interface Electrically Erasable Programmable Read Only Memory (EEPROM)


NM25C04 ,4096-Bit CMOS Serial Interface Electrically Erasable Programmable Read Only Memory (EEPROM)NM25C044096-BitSerialInterfaceCMOSEEPROM(SerialPeripheralInterface(SPI)SynchronousBus)December1993N ..
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NM25C04
4096-Bit CMOS Serial Interface Electrically Erasable Programmable Read Only Memory (EEPROM)
TL/D/11364
NM25C04
4096-Bit
Serial
Interface
CMOS
EEPROM
(Serial
Peripheral
Interface
(SPI)
Synchronous
Bus)
December 1993
NM25C04 4096-Bit Serial Interface CMOS EEPROM
(Serial Peripheral Interface (SPITM) Synchronous Bus)
General Description
The NM25C04isa 4096-bit SPI compatible CMOS
EEPROM. The NM25C04is designedfor data storagein
applications requiring both non-volatile memoryand in-sys-
tem data updates. This EEPROMis well suitedfor applica-
tions usingthe 68HC11 seriesof microcontrollers that sup-
porttheSPI protocolfor high speed communication with
peripheral devicesviaa serialbusto reducepin count.The
NM25C04is implementedin National Semiconductor’ssin-
gle poly, double metal CMOS process which provides supe-
rior enduranceand data retention.
The serial data transmissionofthis device requiresfoursig-
nal linesto controlthe device operation: Chip Select (CS),
Clock (SCK), Serial DataIn (SI), and Serial DataOut (SO).
All programming cyclesare completely self-timed anddo
not requirean erase before WRITE.
BLOCK WRITE protectionis providedby programmingthe
STATUS REGISTERwithoneoffour levelsof write protec-
tion. Additionally, separate program enable and program
disable instructionsare providedfor data protection.
Hardware data protectionis providedbytheWPpinto pro-
tect against accidental data changes.The HOLDpin allows
the serial communicationtobe suspended without resetting
the serial sequence.
Features 4096bits organizedas512 bytes Multiple chipsonthe same 3-wire bus with separate
chip select lines Self-timed programming cycle Simultaneous programmingof1to4 bytesata time Status register canbe polled during programmingto
monitor RDY/BUSY Write Protect (WP)pin and write disable instructionfor
both hardwareand software write protection Block write protect featureto protect against accidental
writes Endurance:106 data changes Data retention greater than40 years Packages available: 8-pinDIPor 8-pinSO
Block Diagram
TL/D/11364–1
SPITM isatrademark ofMotorola Corporation.
C1995National SemiconductorCorporation RRD-B30M65/PrintedinU.S.A.
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