NLSF308MNR2 ,Quad 2-Input AND Gatemaintaining CMOS low power dissipation.The internal circuit is composed of three stages, including ..
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NLSF308MNR2
Quad 2-Input AND Gate
maintaining CMOS low power dissipation.The internal circuit is composed of three stages, including a bufferMARKINGoutput which provides high noise immunity and stable output. TheDIAGRAMinputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 Vsystems to 3.0 V systems.16• High Speed: t = 4.3 ns (Typ) at V = 5.0 VPD CC1NLSF• Low Power Dissipation: I = 2.0 A (Max) at T = 25°CCC A308QFN−16• High Noise Immunity: V = V = 28% VNIH NIL CC ALYWMN SUFFIX• Power Down Protection Provided on InputsCASE 485G• Balanced Propagation Delays(Top View)• Designed for 2.0 V to 5.5 V Operating RangeA = Assembly Location• Low Noise: V = 0.8 V (Max)WL, L = Wafer LotOLPYY, Y = Year• Function Compatible with Other Standard Logic FamiliesWW, W = Work Week• QFN−16 Package• Latchup Performance Exceeds 300 mAORDERING INFORMATION• ESD Performance: Human Body Model; > 2000 V;Device Package Shipping†Machine Model; > 200 VNLSF308MN QFN−16, 3x3 123 Units/Rail• Chip Complexity: 24 FETs or 6 Equivalent GatesNLSF308MNR2 QFN−16, 3x3 3000/Tape & Reel†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationsBrochure, BRD8011/D. Semiconductor Components Industries, LLC, 20041 Publication Order Number:March, 2004 − Rev. 2 NLSF308/DB4 A3Y3VCCGNDA1B1 Y2NLSF30815A11Y116FUNCTION TABLEB1Inputs Output3A25AB YY24B2L L LY = AB8 L H LA37H L LY39H H HB312A410Y413B4Figure 1.
