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NDS8961
Dual N-Channel Enhancement Mode Field Effect Transistor
September 1996
ADVANCE INFORMATION
NDS8961
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description Features_______________________________________________________________________________________________
Absolute Maximum Ratings TA = 25°C unless otherwise note
Symbol Parameter NDS8961 UnitsDSS Drain-Source Voltage 30 V
VGSS Gate-Source Voltage ±20 VD Drain Current - Continuous (Note 1a) 3.1 A
- Pulsed 9 Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9J,TSTG Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICSθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/WθJC Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
SO-8 N-Channel enhancement mode power field
effect transistors are produced using National's
proprietary, high cell density, DMOS technology.
This very high density process is especially tailored
to minimize on-state resistance and provide superior
switching performance. These devices are
particularly suited for low voltage applications such
as DC motor control and DC/DC conversion where
fast switching, low in-line power loss, and resistance
to transients are needed.
3.1A, 30V. R DS(ON) = 0.1Ω @ VGS = 10V
R DS(ON) = 0.15Ω @ VGS = 4.5V.
High density cell design for extremely low RDS(ON).
High power and current handling capability in a
widely used surface mount package.
Dual MOSFET in surface mount package.
