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NDS356
P-Channel Logic Level Enhancement Mode Field Effect Transistor
September 1996 NDS356AP P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features TM -1.1 A, -30 V, R = 0.3 W @ V =-4.5 V SuperSOT -3 P-Channel logic level enhancement mode DS(ON) GS power field effect transistors are produced using Fairchild's R = 0.2 W @ V =-10 V. DS(ON) GS proprietary, high cell density, DMOS technology. This very high Industry standard outline SOT-23 surface mount package density process is especially tailored to minimize on-state TM using proprietary SuperSOT -3 design for superior resistance. These devices are particularly suited for low voltage thermal and electrical capabilities. applications such as notebook computer power management, portable electronics, and other battery powered circuits where High density cell design for extremely low R . DS(ON) fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. Exceptional on-resistance and maximum DC current capability. ________________________________________________________________________________ D S G Absolute Maximum Ratings T = 25°C unless otherwise noted A Symbol Parameter NDS356AP Units V Drain-Source Voltage -30 V DSS V Gate-Source Voltage - Continuous ±20 V GSS I Maximum Drain Current - Continuous (Note 1a) ±1.1 A D - Pulsed ±10 P Maximum Power Dissipation (Note 1a) 0.5 W D (Note 1b) 0.46 T ,T Operating and Storage Temperature Range -55 to 150 °C J STG THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W R JA q Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W R JC q © 1997 NDS356AP Rev.C1
