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NDS355N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
March 1996 NDS355N N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These N-Channel logic level enhancement mode power field 1.6A, 30V. R = 0.125W @ V = 4.5V. DS(ON) GS effect transistors are produced using Fairchild's proprietary, Proprietary package design using copper lead frame for high cell density, DMOS technology. This very high density superior thermal and electrical capabilities. process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage High density cell design for extremely low R . DS(ON) applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching, Exceptional on-resistance and maximum DC current and low in-line power loss are needed in a very small outline capability. surface mount package. Compact industry standard SOT-23 surface mount package. _______________________________________________________________________________ D G S Absolute Maximum Ratings T = 25°C unless otherwise noted A Symbol Parameter NDS355N Units V Drain-Source Voltage 30 V DSS V Gate-Source Voltage - Continuous 20 V GSS I Drain Current - Continuous (Note 1a) ± 1.6 A D - Pulsed ± 10 P Maximum Power Dissipation (Note 1a) 0.5 W D (Note 1b) 0.46 T ,T Operating and Storage Temperature Range -55 to 150 °C J STG THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W R JA q Thermal Resistance, Junction-to -Case (Note 1) 75 °C/W R JC q © 1997 NDS355N Rev. D1
