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NDS332NASN/a24000avaiP-Channel Logic Level Enhancement Mode Field Effect Transistor


NDS332 ,P-Channel Logic Level Enhancement Mode Field Effect TransistorElectrical Characteristics (T = 25°C unless otherwise noted)ASymbol Parameter Conditions Min Typ Ma ..
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NDS332
P-Channel Logic Level Enhancement Mode Field Effect Transistor
June 1997 NDS332P P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features -1 A, -20 V,  R = 0.41 W @ V = -2.7 V These P-Channel logic level enhancement mode power field DS(ON) GS effect transistors are produced using Fairchild's proprietary, high R = 0.3 W @ V = -4.5 V. DS(ON) GS cell density, DMOS technology. This very high density process is Very low level gate drive requirements allowing direct especially tailored to minimize on-state resistance. These operation in 3V circuits. V < 1.0V. devices are particularly suited for low voltage applications such as GS(th) notebook computer power management, portable electronics, Proprietary package design using copper lead frame for and other battery powered circuits where fast high-side superior thermal and electrical capabilities. switching, and low in-line power loss are needed in a very small outline surface mount package. High density cell design for extremely low R . DS(ON) Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface Mount package. ________________________________________________________________________________ D G S Asolute Maximum Ratings T = 25°C unless otherwise noted A Symbol Parameter NDS332P Units V Drain-Source Voltage -20 V DSS V Gate-Source Voltage - Continuous ±8 V GSS I Drain Current - Continuous (Note 1a) -1 A D - Pulsed -10 P Maximum Power Dissipation (Note 1a) 0.5 W D (Note 1b) 0.46 T ,T Operating and Storage Temperature Range -55 to 150 °C J STG THERMAL CHARACTERISTICS R Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W JA q R Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W JC q © 1997 NDS332P Rev. E
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