NDP4050L ,N-Channel Logic Level Enhancement Mode Field Effect Transistorapplications._______________________________________________________________________________ DGSAbs ..
NDP4050L ,N-Channel Logic Level Enhancement Mode Field Effect TransistorElectrical Characteristics (T = 25°C unless otherwise noted)CSymbol Parameter Conditions Min Typ Ma ..
NDP4060 ,N-Channel Enhancement Mode Field Effect Transistorapplications. _____________________________________________________________________________________ ..
NDP4060 ,N-Channel Enhancement Mode Field Effect TransistorElectrical Characteristics (T = 25°C unless otherwise noted)CSymbol Parameter Conditions Min Typ Ma ..
NDP4060L ,N-Channel Logic Level Enhancement Mode Field Effect Transistorapplications.________________________________________________________________________________ DGSAb ..
NDP4060L ,N-Channel Logic Level Enhancement Mode Field Effect TransistorElectrical Characteristics (T = 25°C unless otherwise noted)CSymbol Parameter Conditions Min Typ Ma ..
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NDP4050L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
April 1996 NDP4050L / NDB4050L N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These logic level N-Channel enhancement mode power field 15A, 50V. R = 0.1W @ V = 5V DS(ON) GS effect transistors are produced using Fairchild's proprietary, Low drive requirements allowing operation directly from logic high cell density, DMOS technology. This very high density drivers. V < 2.0V. GS(TH) process has been especially tailored to minimize on-state resistance, provide superior switching performance, and Critical DC electrical parameters specified at elevated withstand high energy pulses in the avalanche and temperature. commutation modes. These devices are particularly suited for Rugged internal source-drain diode can eliminate the need low voltage applications such as automotive, DC/DC for an external Zener diode transient suppressor. converters, PWM motor controls, and other battery powered circuits where fast switching, low in-line power loss, and 175°C maximum junction temperature rating. resistance to transients are needed. High density cell design for extremely low R . DS(ON) 2 TO-220 and TO-263 (D PAK) package for both through hole and surface mount applications. _______________________________________________________________________________ D G S Absolute Maximum Ratings T = 25°C unless otherwise noted C Symbol Parameter NDP4050L NDB4050L Units V Drain-Source Voltage 50 V DSS V 50 V Drain-Gate Voltage (R < 1 MW) DGR GS V Gate-Source Voltage - Continuous ± 16 V GSS - Nonrepetitive (t < 50 µs) ± 25 P Drain Current - Continuous 15 A I D - Pulsed 45 P Total Power Dissipation @ T = 25°C 50 W D C Derate above 25°C 0.33 W/°C T ,T Operating and Storage Temperature -65 to 175 °C J STG T Maximum lead temperature for soldering 275 °C L purposes, 1/8" from case for 5 seconds © 1997 NDP4050L Rev. B / NDB4050L Rev. C
