NDH8521C ,Dual N & P-Channel Enhancement Mode Field Effect TransistorElectrical Characteristics (T = 25°C unless otherwise noted)ASymbol Parameter Conditions Type Min T ..
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NDH8521C
Dual N & P-Channel Enhancement Mode Field Effect Transistor
May 1997 NDH8521C Dual N & P-Channel Enhancement Mode Field Effect Transistor General Description Features These dual N- and P-Channel enhancement mode power field N-Ch 3.8 A, 30 V, R =0.033W @ V =10 V DS(ON) GS effect transistors are produced using Fairchild's proprietary, R =0.05 W @ V =4.5 V DS(ON) GS high cell density, DMOS technology. This very high density P-Ch -2.7 A, -30 V,R =0.07 W @ V =-10 V DS(ON) GS process is especially tailored to minimize on-state resistance R =0.115 W @ V =-4.5 V. and provide superior switching performance. These devices DS(ON) GS are particularly suited for low voltage applications such as TM Proprietary SuperSOT -8 package design using copper lead notebook computer power management and other battery frame for superior thermal and electrical capabilities. powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. High density cell design for extremely low R . DS(ON) Exceptional on-resistance and maximum DC current capability. ________________________________________________________________________________ 4 5 6 3 2 7 8 1 Absolute Maximum Ratings T = 25°C unless otherwise noted A Symbol Parameter N-Channel P-Channel Units V Drain-Source Voltage 30 -30 V DSS Gate-Source Voltage ±20 ±20 V V GSS Drain Current - Continuous (Note 1) 3.8 -2.7 A I D - Pulsed 10.5 -8 P Power Dissipation for Single Operation (Note 1) 0.8 W D T ,T Operating and Storage Temperature Range -55 to 150 °C J STG THERMAL CHARACTERISTICS R Thermal Resistance, Junction-to-Ambient (Note 1) 156 °C/W qJA R Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W qJC © 1997 NDH8521C Rev.C
