NDC7001C ,Dual N & P-Channel Enhancement Mode Field Effect Transistorapplications. • High saturation current • High density cell design for low R DS(ON)TM• Proprietary ..
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NDC7001C
Dual N & P-Channel Enhancement Mode Field Effect Transistor
NDC7001C May 2002 NDC7001C Dual N & P-Channel Enhancement Mode Field Effect Transistor General Description Features These dual N & P-Channel Enhancement Mode Field • Q1 0.51 A, 60V. RDS(ON) = 2 Ω @ VGS = 10 V Effect Transistors are produced using Fairchild’s RDS(ON) = 4 Ω @ VGS = 4.5 V proprietary, high cell density, DMOS technology. This very high density process has been designed to • Q2 –0.34 A, 60V. R = 5 Ω @ V = –10 V DS(ON) GS minimize on-state resistance, provide rugged and reliable performance and fast switching. These R = 7.5Ω @ V = –4.5 V DS(ON) GS device is particularly suited for low voltage, low current, switching, and power supply applications. • High saturation current • High density cell design for low R DS(ON) TM • Proprietary SuperSOT –6 package: design using copper lead frame for superior thermal and electrical capabilities D2 Q2(P) S1 4 3 D1 5 2 G2 1 6 S2 TM SuperSOT -6 Q1(N) G1 o Absolute Maximum Ratings T =25 C unless otherwise noted A Symbol Parameter Q1 Q2 Units V Drain-Source Voltage 60 –60 V DSS V Gate-Source Voltage ±20 ±20 GSS I Drain Current – Continuous (Note 1a) 0.51 –0.34 A D – Pulsed 1.5 –1 Power Dissipation for Single Operation (Note 1a) 0.96 P D (Note 1b) W 0.9 (Note 1c) 0.7 T , T Operating and Storage Junction Temperature Range –55 to +150 J STG °C Thermal Characteristics °C/W R Thermal Resistance, Junction-to-Ambient (Note 1a) 130 θJA Thermal Resistance, Junction-to-Case (Note 1) 60 R θJC Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity .01C NDC7001C 7’’ 8mm 3000 NDC7001C Rev B (W) 2002
