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NDB6030PL_NL
P-Channel Logic Level Enhancement Mode Field Effect Transistor
June 1997 NDP6030PL / NDB6030PL P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These P-Channel logic level enhancement mode power field -30 A, -30 V. R = 0.042 W @ V = -4.5 V DS(ON) GS effect transistors are produced using Fairchild's proprietary, R = 0.025 W @ V = -10 V. DS(ON) GS high cell density, DMOS technology. This very high density Critical DC electrical parameters specified at elevated process is especially tailored to minimize on-state resistance. temperature. These devices are particularly suited for low voltage applications such as DC/DC converters and high efficiency Rugged internal source-drain diode can eliminate the need switching circuits where fast switching, low in-line power loss, for an external Zener diode transient suppressor. and resistance to transients are needed. High density cell design for extremely low R . DS(ON) 175°C maximum junction temperature rating. ________________________________________________________________________________ S G D Absolute Maximum Ratings T = 25°C unless otherwise noted C Symbol Parameter NDP6030PL NDB6030PL Units V Drain-Source Voltage -30 V DSS V Gate-Source Voltage - Continuous ±16 V GSS I Drain Current - Continuous -30 A D - Pulsed -90 P Total Power Dissipation @ T = 25°C 75 W D C Derate above 25°C 0.5 Operating and Storage Temperature Range -65 to 175 °C T ,T J STG T Maximum lead temperature for soldering purposes, 275 °C L 1/8" from case for 5 seconds T ,T Operating and Storage Temperature Range -65 to 175 °C J STG THERMAL CHARACTERISTICS R Thermal Resistance, Junction-to-Case 2 °C/W JC q R Thermal Resistance, Junction-to-Ambient 62.5 °C/W qJA © 1997 NDP6030PL Rev.B1
