NC7SZ38P5X ,TinyLogic UHS 2-Input NAND Gate (Open Drain Output)NC7SZ38 TinyLogic UHS 2-Input NAND Gate (Open Drain Output)October 1996Revised August 2004NC7SZ38T ..
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NC7SZ38L6X-NC7SZ38M5X-NC7SZ38P5X
TinyLogic UHS 2-Input NAND Gate (Open Drain Output)
NC7SZ38 TinyLogic UHS 2-Input NAND Gate (Open Drain Output) October 1996 Revised August 2004 NC7SZ38 TinyLogic UHS 2-Input NAND Gate (Open Drain Output) General Description Features The NC7SZ38 is a single 2-Input NAND Gate with openSpace saving SOT23 or SC70 5-lead package drain output stage from Fairchild’s Ultra High Speed SeriesUltra small MicroPak leadless package of TinyLogic. The device is fabricated with advanced Open Drain output stage for OR tied applications CMOS technology to achieve ultra high speed with high Ultra High Speed; t 2.4 ns Typ into 50 pF at 5V V output drive while maintaining low static power dissipation PD CC over a very broad V operating range. The device isHigh Output Sink Drive; 24 mA at 3V V CC CC specified to operate over the 1.65V to 5.5V V range. The CCBroad V Operating Range; 1.65V to 5.5V CC inputs and output are high impedance when V is 0V. CC Matches the performance of LCX when operated at Inputs tolerate voltages up to 6V independent of V oper- CC 3.3V V CC ating voltage. The open drain output stage will tolerate volt- Power down high impedance inputs/output ages up to 6V independent of V when in the high CC Overvoltage Tolerant inputs facilitate 5V to 3V impedance state. translation Patented noise/EMI reduction circuitry implemented Ordering Code: Order Package Product Code Package Description Supplied As Number Number Top Mark NC7SZ38M5X MA05B 7Z38 5-Lead SOT23, JEDEC MO-178, 1.6mm 3k Units on Tape and Reel NC7SZ38P5X MAA05A Z38 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3k Units on Tape and Reel NC7SZ38L6X MAC06A A6 6-Lead MicroPak, 1.0mm Wide 5k Units on Tape and Reel Pin Descriptions Logic Symbol Pin Names Description IEEE/IEC A, B Inputs Y Output NC No Connect Connection Diagrams Function Table Pin Assignments for SC70 and SOT23 Y = AB Inputs Output AB Y LL *H LH *H HL *H (Top View) HH L Pad Assignment for MicroPak H = HIGH Logic Level L = LOW Logic Level *H = HIGH Impedance output state (Open Drain) (Top Thru View) TinyLogic is a registered trademark of . MicroPak is a trademark of . © 2004 DS012175
