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NC7SZ157L6XFAIRCHILDN/a735avaiTinyLogic UHS 2-Input Non-Inverting Multiplexer
NC7SZ157P6XFAIN/a1270avaiTinyLogic UHS 2-Input Non-Inverting Multiplexer
NC7SZ157P6X_NLFAIRCHILN/a1600avaiTinyLogic UHS 2-Input Non-Inverting Multiplexer
NC7SZ157P6X_NL |NC7SZ157P6XNLFAIRCHILDN/a6000avaiTinyLogic UHS 2-Input Non-Inverting Multiplexer


NC7SZ157P6X_NL ,TinyLogic UHS 2-Input Non-Inverting MultiplexerNC7SZ157 TinyLogic UHS 2-Input Non-Inverting MultiplexerApril 2000Revised August 2004NC7SZ157TinyL ..
NC7SZ157P6X_NL ,TinyLogic UHS 2-Input Non-Inverting MultiplexerFeaturesThe NC7SZ157 is a single, high performance, 2 to 1

NC7SZ157L6X-NC7SZ157P6X-NC7SZ157P6X_NL
TinyLogic UHS 2-Input Non-Inverting Multiplexer
NC7SZ157 TinyLogic UHS 2-Input Non-Inverting Multiplexer April 2000 Revised August 2004 NC7SZ157 TinyLogic UHS 2-Input Non-Inverting Multiplexer General Description Features The NC7SZ157 is a single, high performance, 2 to 1Space saving SC70-6 lead surface mount package CMOS non-inverting multiplexer from Fairchild’s Ultra HighUltra Small MicroPak leadless package Speed Series of TinyLogic. The device is fabricated with Ultra High Speed advanced CMOS technology to achieve ultra high speed Broad V operating range: 1.65V to 5.5V with high output drive while maintaining low static power CC dissipation over a broad V operating range. The devicePower down high impedance input/output CC is specified to operate over the 1.65V to 5.5V V operat- CCOvervoltage tolerant inputs facilitate 5V to 3V translation ing range. The inputs and outputs are high impedance Patented noise/EMI reduction circuitry implemented when V is 0V. Inputs tolerate voltages up to 5.5V inde- CC pendent of V operating range. CC Ordering Code: Order Package Package Package Description Supplied As Number Number Top Mark NC7SZ157P6X MAA06A ZF7 6-Lead SC70, EIAJ SC88, 1.25mm Wide 3k Units on Tape and Reel NC7SZ157L6X MAC06A B9 6-Lead MicroPak, 1.0mm Wide 5k Units on Tape and Reel Logic Symbol Connection Diagram IEEE/IEC (Top View) Function Table Pin One Orientation Diagram Inputs Output S I I Z = (I )•(S)+(I )(S) 1 0 0 1 LX L L LX H H AAA = Product Code Top Mark - see ordering code HL X L Note: Orientation of Top Mark determines Pin One location. Read the top HH X H product code mark left to right, Pin One is the lower left pin (see diagram). H = HIGH Logic Level L = LOW Logic Level Pad Assignments for MicroPak Pin Descriptions Pin Name Description I , I Data Inputs 0 1 S Control Input Z Output (Top Thru View) TinyLogic is a registered trademark of . MicroPak is a trademark of . © 2004 DS500359
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