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NC7NZ34K8XFAIRCHILDN/a12000avaiTinyLogic UHS Triple Buffer
NC7NZ34L8XFSCN/a985avaiTinyLogic UHS Triple Buffer
NC7NZ34L8XFAIRCHILDN/a5192avaiTinyLogic UHS Triple Buffer


NC7NZ34K8X ,TinyLogic UHS Triple BufferFeaturesThe NC7NZ34 is a triple buffer from Fairchild’s Ultra High

NC7NZ34K8X-NC7NZ34L8X
TinyLogic UHS Triple Buffer
NC7NZ34 TinyLogic UHS Triple Buffer July 2001 Revised January 2005 NC7NZ34 TinyLogic UHS Triple Buffer General Description Features The NC7NZ34 is a triple buffer from Fairchild’s Ultra HighSpace saving US8 surface mount package Speed Series of TinyLogic in the space saving US8 pack-MicroPak Pb-Free leadless package age. The device is fabricated with advanced CMOS tech- Ultra High Speed: t 2.4 ns Typ into 50 pF at 5V V PD CC nology to achieve ultra high speed with high output drive High Output Drive: ±24 mA at 3V V while maintaining low static power dissipation over a very CC broad V operating range. The device is specified to CCBroad V Operating Range: 1.65V to 5.5V CC operate over the 1.65V to 5.5V V range. The inputs and CC Power down high impedance inputs/outputs outputs are high impedance when V is 0V. Inputs toler- CC Overvoltage tolerant inputs facilitate 5V to 3V translation ate voltages up to 7V independent of V operating volt- CC Patented noise/EMI reduction circuitry implemented age. Ordering Code: Product Order Package Code Package Description Supplied As Number Number Top Mark NC7NZ34K8X MAB08A 7NZ34 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel NC7NZ34L8X MAC08A P9 Pb-Free 8-Lead MicroPak, 1.6 mm Wide 5k Units on Tape and Reel Pb-Free package per JEDEC J-STD-020B. Logic Symbol Connection Diagrams IEEE/IEC (Top View) Pin Descriptions Pin One Orientation Diagram Pin Names Description A , A , A Data Inputs 1 2 3 Y , Y , Y Output 1 2 3 Function Table AAA represents Product Code Top Mark - see ordering code Note: Orientation of Top Mark determines Pin One location. Read the top Y = A product code mark left to right, Pin One is the lower left pin (see diagram). Input Output Pad Assignments for MicroPak AY LL HH H = HIGH Logic Level L = LOW Logic Level (Top Thru View) TinyLogic is a registered trademark of . MicroPak is a trademark of . © 2005 DS500494
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