NB6N239S ,3.3V, 3.0 GHz Any Differential Clock IN to LVDS OUT Div 1/2/4/8, Div 2/4/8/16 Clock DividerLogic Diagram Semiconductor Components Industries, LLC, 20131 Publication Order Number:January, 20 ..
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NB6N239S
3.3V, 3.0 GHz Any Differential Clock IN to LVDS OUT Div 1/2/4/8, Div 2/4/8/16 Clock Divider
NB6N239S
3.3 V , 3.0 GHz Any
Differential Clock IN to
LVDS OUT ÷1/2/4/8, ÷2/4/8/16
Clock Divider
Description
The NB6N239S is a highïspeed, low skew clock divider with two
divider circuits, each having selectable clock divide ratios; 1/2/4/8
and 2/4/8/16. Both divider circuits drive LVDS compatible outputs.
(More device information on page 7). The NB6N239S is a member
of the ECLinPS MAX family of high performance clock products.
Features Maximum Clock Input Frequency, 3.0 GHz (1.5 GHz with 1) Input Compatibility with LVDS/LVPECL/CML/HSTL/HCSL Rise/Fall Time 120 ps Typical < 5 ps Typical Within Device Output Skew Example; 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz
Outputs Internal 50 Termination Provided Random Clock Jitter < 2 ps RMS QA 1 Edge Aligned to QB n Edge Operating Range: VCC = 3.0 V to 3.465 V with GND = 0 V Master Reset for Synchronization of Multiple Chips VBBAC Reference Output Synchronous Output Enable/Disable TIA/EIA ï 644 Compliant These Devices are PbïFree and are RoHS Compliant
CLK
CLK
SELB1
SELB0
SELA1
SELA0
16
VBBAC
MARKING DIAGRAM*
QFNï16
MN SUFFIX
CASE 485G = Assembly Location = Wafer Lot = Year = Work Week = PbïFree Package
Bottom View
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
http://
(Note: Microdot may be in either location)
NB6N
239S
ALYW
