NAND512W3A0AN6E ,128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash MemoriesBlock Diagram . . . . . 9Figure 4. TSOP48 and USOP48 Connections, x8 devices . . . . . . . ..
NAND512W3A2BN6E , 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512W3A2BN6E , 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512W3A2BN6E , 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512W3A2BZB6E , 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512W3A2BZB6F , 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NJM13404V , SINGLE SUPPRY QUAD OPERATIONAL AMPLIFIER
NJM13700M , DUAL OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
NJM1372AD , TV VIDEO MODULATOR
NJM1431AF , ADJUSTABLE HIGH PRECISION SHUNT REGULATOR
NJM1431AU , ADJUSTABLE HIGH PRECISION SHUNT REGULATOR
NJM14558 , DUAL OPERATIONAL AMPLIFIER
NAND256W3A0AN6-NAND512W3A0AN6-NAND512W3A0AN6E
128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
1/57February 2005
NAND128-A, NAND256-A
NAND512-A, NAND01G-A128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16)
528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES Up to 1 Gbit memory array Up to 32 Mbit spare area Cost effective solutions for mass storage
applications NAND INTERFACE x8 or x16 bus width Multiplexed Address/ Data Pinout compatibility for all densities SUPPLY VOLTAGE 1.8V device: VDD = 1.7 to 1.95V 3.0V device: VDD = 2.7 to 3.6V PAGE SIZE x8 device: (512 + 16 spare) Bytes x16 device: (256 + 8 spare) Words BLOCK SIZE x8 device: (16K + 512 spare) Bytes x16 device: (8K + 256 spare) Words PAGE READ / PROGRAM Random access: 12µs (max) Sequential access: 50ns (min) Page program time: 200µs (typ) COPY BACK PROGRAM MODE Fast page copy without external buffering FAST BLOCK ERASE Block erase time: 2ms (Typ) STATUS REGISTER ELECTRONIC SIGNATURE CHIP ENABLE ‘DON’T CARE’ OPTION Simple interface with microcontroller SERIAL NUMBER OPTION HARDWARE DATA PROTECTION Program/Erase locked during Power
transitions
Figure 1. Packages DATA INTEGRITY 100,000 Program/Erase cycles 10 years Data Retention RoHS COMPLIANCE Lead-Free Components are Compliant
with the RoHS Directive DEVELOPMENT TOOLS Error Correction Code software and
hardware models Bad Blocks Management and Wear
Leveling algorithms File System OS Native reference software Hardware simulation models
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 1. Product List
3/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 2. Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 3. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 3. Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 4. TSOP48 and USOP48 Connections, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 5. TSOP48 and USOP48 Connections, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 6. FBGA55 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . .11
Figure 7. FBGA55 Connections, x16 devices (Top view through package) . . . . . . . . . . . . . . . . . .12
Figure 8. FBGA63 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . .13
Figure 9. FBGA63 Connections, x16 devices (Top view through package) . . . . . . . . . . . . . . . . . .14
MEMORY ARRAY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Bad Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 4. Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 10.Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Inputs/Outputs (I/O0-I/O7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Inputs/Outputs (I/O8-I/O15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Read Enable (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
VDD Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 5. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 6. Address Insertion, x8 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
NAND128-A, NAND256-A, NAND512-A, NAND01G-ATable 7. Address Insertion, x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 8. Address Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DEVICE OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Figure 11.Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 12.Pointer Operations for Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Read Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Sequential Row Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 13.Read (A,B,C) Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 14.Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 15.Sequential Row Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 16.Sequential Row Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Figure 17.Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 10. Copy Back Program Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 18.Copy Back Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Figure 19.Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
P/E/R Controller Bit (SR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Error Bit (SR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
SR5, SR4, SR3, SR2 and SR1 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Table 12. Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
SOFTWARE ALGORITHMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Table 13. Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 20.Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 21.Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Wear-leveling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Error Correction Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Figure 22.Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Hardware Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-ABehavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Table 14. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . .33
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Table 15. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Table 16. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 17. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 18. DC Characteristics, 1.8V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 19. DC Characteristics, 3V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 20. AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 21. AC Characteristics for Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 23.Command Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 24.Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 25.Data Input Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 26.Sequential Data Output after Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 27.Read Status Register AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 28.Read Electronic Signature AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 29.Page Read A/ Read B Operation AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 30.Read C Operation, One Page AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 31.Page Program AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 32.Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 33.Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Ready/Busy Signal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46Figure 34.Ready/Busy AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 35.Ready/Busy Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 36.Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . .46
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47Figure 37.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . .47
Table 22. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data .47
Figure 38.USOP48 – lead Plastic Ultra Thin Small Outline,12 x 17mm, Package Outline . . . . . . .48
Table 23. USOP48 – lead Plastic Ultra Thin Small Outline, 12 x 17mm, Package Mechanical Data48
Figure 39.VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . .49
Table 24. VFBGA55 8 x 10mm - 6x8 ball array, 0.80mm pitch, Package Mechanical Data . . . . . .49
Figure 40.TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline . . . . . . . .50
Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data50
Figure 41.VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . .51
Table 26. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data. .51
Figure 42.TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline. . . . . . . . . .52
Table 27. TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data. .52
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53Table 28. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
APPENDIX A.HARDWARE INTERFACE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54Figure 43.Connection to Microcontroller, Without Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 44.Connection to Microcontroller, With Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 45.Building Storage Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
7/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
SUMMARY DESCRIPTIONThe NAND Flash 528 Byte/ 264 Word Page is a
family of non-volatile Flash memories that uses
the Single Level Cell (SLC) NAND cell technology.
It is referred to as the Small Page family. The de-
vices range from 128Mbits to 1Gbit and operate
with either a 1.8V or 3V voltage supply. The size of
a Page is either 528 Bytes (512 + 16 spare) or 264
Words (256 + 8 spare) depending on whether the
device has a x8 or x16 bus width.
The address lines are multiplexed with the Data In-
put/Output signals on a multiplexed x8 or x16 In-
put/Output bus. This interface reduces the pin
count and makes it possible to migrate to other
densities without changing the footprint.
Each block can be programmed and erased over
100,000 cycles. To extend the lifetime of NAND
Flash devices it is strongly recommended to imple-
ment an Error Correction Code (ECC). A Write
Protect pin is available to give a hardware protec-
tion against program and erase operations.
The devices feature an open-drain Ready/Busy
output that can be used to identify if the Program/
Erase/Read (P/E/R) Controller is currently active.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor.
A Copy Back command is available to optimize the
management of defective blocks. When a Page
Program operation fails, the data can be pro-
grammed in another page without having to re-
send the data to be programmed.
The devices are available in the following packag-
es: TSOP48 12 x 20mm for all products USOP48 12 x 17 x 0.65mm for 128Mb, 256Mb
and 512Mb products VFBGA55 (8 x 10 x 1mm, 6 x 8 ball array,
0.8mm pitch) for 128Mb and 256Mb products TFBGA55 (8 x 10 x 1.2mm, 6 x 8 ball array,
0.8mm pitch) for 512Mb Dual Die product VFBGA63 (9 x 11 x 1mm, 6 x 8 ball array,
0.8mm pitch) for the 512Mb product TFBGA63 (9 x 11 x 1.2mm, 6 x 8 ball array,
0.8mm pitch) for the 1Gb Dual Die product
Two options are available for the NAND Flash
family:
Chip Enable Don’t Care, which allows code to be
directly downloaded by a microcontroller, as Chip
Enable transitions during the latency time do not
stop the read operation.
A Serial Number, which allows each device to be
uniquely identified. The Serial Number options is
subject to an NDA (Non Disclosure Agreement)
and so not described in the datasheet. For more
details of this option contact your nearest ST Sales
office.
For information on how to order these options refer
to Table 28., Ordering Information Scheme. De-
vices are shipped from the factory with Block 0 al-
ways valid and the memory content bits, in valid
blocks, erased to ’1’.
See Table 2., Product Description, for all the de-
vices available in the family.
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 2. Product DescriptionNote:1. Dual Die device.
Figure 2. Logic Diagram Table 3. Signal Names
9/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 3. Logic Block Diagram
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 5. TSOP48 and USOP48 Connections,
x16 devices
11/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 6. FBGA55 Connections, x8 devices (Top view through package)
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 7. FBGA55 Connections, x16 devices (Top view through package)
13/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 8. FBGA63 Connections, x8 devices (Top view through package)
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 9. FBGA63 Connections, x16 devices (Top view through package)
15/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
MEMORY ARRAY ORGANIZATIONThe memory array is made up of NAND structures
where 16 cells are connected in series.
The memory array is organized in blocks where
each block contains 32 pages. The array is split
into two areas, the main area and the spare area.
The main area of the array is used to store data
whereas the spare area is typically used to store
Error correction Codes, software flags or Bad
Block identification.
In x8 devices the pages are split into a main area
with two half pages of 256 Bytes each and a spare
area of 16 Bytes. In the x16 devices the pages are
split into a 256 Word main area and an 8 Word
spare area. Refer to Figure 10., Memory Array Or-
ganization.
Bad BlocksThe NAND Flash 528 Byte/ 264 Word Page devic-
es may contain Bad Blocks, that is blocks that con-
tain one or more invalid bits whose reliability is not
guaranteed. Additional Bad Blocks may develop
during the lifetime of the device.
The Bad Block Information is written prior to ship-
ping (refer to Bad Block Management section for
more details).
Table 4. shows the minimum number of valid
blocks in each device. The values shown include
both the Bad Blocks that are present when the de-
vice is shipped and the Bad Blocks that could de-
velop later on.
These blocks need to be managed using Bad
Blocks Management, Block Replacement or Error
Correction Codes (refer to SOFTWARE ALGO-
RITHMS section).
Table 4. Valid Blocks
Figure 10. Memory Array Organization
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
SIGNAL DESCRIPTIONSSee Figure 2., Logic Diagram, and Table
3., Signal Names, for a brief overview of the sig-
nals connected to this device.
Inputs/Outputs (I/O0-I/O7). Input/Outputs 0 to 7
are used to input the selected address, output the
data during a Read operation or input a command
or data during a Write operation. The inputs are
latched on the rising edge of Write Enable. I/O0-I/
O7 are left floating when the device is deselected
or the outputs are disabled.
Inputs/Outputs (I/O8-I/O15). Input/Outputs 8 to
15 are only available in x16 devices. They are
used to output the data during a Read operation or
input data during a Write operation. Command and
Address Inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write
Enable. I/O8-I/O15 are left floating when the de-
vice is deselected or the outputs are disabled.
Address Latch Enable (AL). The Address Latch
Enable activates the latching of the Address inputs
in the Command Interface. When AL is high, the
inputs are latched on the rising edge of Write En-
able.
Command Latch Enable (CL). The Command
Latch Enable activates the latching of the Com-
mand inputs in the Command Interface. When CL
is high, the inputs are latched on the rising edge of
Write Enable.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
low, VIL, the device is selected.
While the device is busy programming or erasing,
Chip Enable transitions to High, VIH, are ignored
and the device does not revert to the Standby
mode.
While the device is busy reading: the Chip Enable input should be held Low
during the whole busy time (tBLBH1) for
devices that do not present the Chip Enable
Don’t Care option. Otherwise, the read
operation in progress is interrupted and the
device reverts to the Standby mode. for devices that feature the Chip Enable Don't
Care option, Chip Enable going High during
the busy time (tBLBH1) will not interrupt the
read operation and the device will not revert to
the Standby mode.
Read Enable (R). The Read Enable, R, controls
the sequential data output during Read opera-
tions. Data is valid tRLQV after the falling edge of R.
The falling edge of R also increments the internal
column address counter by one.
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data are latched on the rising edge of Write En-
able.
During power-up and power-down a recovery time
of 1µs (min) is required before the Command Inter-
face is ready to accept a command. It is recom-
mended to keep Write Enable high during the
recovery time.
Write Protect (WP). The Write Protect pin is an
input that gives a hardware protection against un-
wanted program or erase operations. When Write
Protect is Low, VIL, the device does not accept any
program or erase operations.
It is recommended to keep the Write Protect pin
Low, VIL, during power-up and power-down.
Ready/Busy (RB). The Ready/Busy output, RB,
is an open-drain output that can be used to identify
if the P/E/R Controller is currently active.
When Ready/Busy is Low, VOL, a read, program or
erase operation is in progress. When the operation
completes Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Refer to the Ready/Busy Signal Electrical Charac-
teristics section for details on how to calculate the
value of the pull-up resistor.
VDD Supply Voltage. VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations (read,
program and erase).
An internal voltage detector disables all functions
whenever VDD is below 2.5V (for 3V devices) or
1.5V (for 1.8V devices) to protect the device from
any involuntary program/erase during power-tran-
sitions.
Each device in a system should have VDD decou-
pled with a 0.1µF capacitor. The PCB track widths
should be sufficient to carry the required program
and erase currents
VSS Ground. Ground, VSS, is the reference for
the power supply. It must be connected to the sys-
tem ground.
17/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
BUS OPERATIONSThere are six standard bus operations that control
the memory. Each of these is described in this
section, see Table 5., Bus Operations, for a sum-
mary.
Command Input Command Input bus operations are used to give
commands to the memory. Command are accept-
ed when Chip Enable is Low, Command Latch En-
able is High, Address Latch Enable is Low and
Read Enable is High. They are latched on the ris-
ing edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 23. and Table 20. for details of the tim-
ings requirements.
Address Input Address Input bus operations are used to input the
memory address. Three bus cycles are required to
input the addresses for the 128Mb and 256Mb de-
vices and four bus cycles are required to input the
addresses for the 512Mb and 1Gb devices (refer
to Tables 6 and 7, Address Insertion).
The addresses are accepted when Chip Enable is
Low, Address Latch Enable is High, Command
Latch Enable is Low and Read Enable is High.
They are latched on the rising edge of the Write
Enable signal. Only I/O0 to I/O7 are used to input
addresses.
See Figure 24. and Table 20. for details of the tim-
ings requirements.
Data InputData Input bus operations are used to input the
data to be programmed.
Data is accepted only when Chip Enable is Low,
Address Latch Enable is Low, Command Latch
Enable is Low and Read Enable is High. The data
is latched on the rising edge of the Write Enable
signal. The data is input sequentially using the
Write Enable signal.
See Figure 25. and Table 20. and Table 21. for de-
tails of the timings requirements.
Data Output Data Output bus operations are used to read: the
data in the memory array, the Status Register, the
Electronic Signature and the Serial Number.
Data is output when Chip Enable is Low, Write En-
able is High, Address Latch Enable is Low, and
Command Latch Enable is Low.
The data is output sequentially using the Read En-
able signal.
See Figure 26. and Table 21. for details of the tim-
ings requirements.
Write Protect Write Protect bus operations are used to protect
the memory against program or erase operations.
When the Write Protect signal is Low the device
will not accept program or erase operations and so
the contents of the memory array cannot be al-
tered. The Write Protect signal is not latched by
Write Enable to ensure protection even during
power-up.
Standby When Chip Enable is High the memory enters
Standby mode, the device is deselected, outputs
are disabled and power consumption is reduced.
Table 5. Bus OperationsNote:1. Only for x16 devices. WP must be VIH when issuing a program or erase command.
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 6. Address Insertion, x8 DevicesNote:1. A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section. Any additional address input cycles will be ignored. The 4th cycle is only required for 512Mb and 1Gb devices.
Table 7. Address Insertion, x16 DevicesNote:1. A8 is Don’t Care in x16 devices. Any additional address input cycles will be ignored. The 01h Command is not used in x16 devices. The 4th cycle is only required for 512Mb and 1Gb devices.
Table 8. Address Definitions
19/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
COMMAND SETAll bus write operations to the device are interpret-
ed by the Command Interface. The Commands
are input on I/O0-I/O7 and are latched on the rising
edge of Write Enable when the Command Latch
Enable signal is high. Device operations are se-
lected by writing specific commands to the Com-
mand Register. The two-step command
sequences for program and erase operations are
imposed to maximize data security.
The Commands are summarized in Table
9., Commands.
Table 9. CommandsNote:1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown. Any undefined command sequence will be ignored by the device.
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
DEVICE OPERATIONS
Pointer OperationsAs the NAND Flash memories contain two differ-
ent areas for x16 devices and three different areas
for x8 devices (see Figure 11.) the read command
codes (00h, 01h, 50h) are used to act as pointers
to the different areas of the memory array (they se-
lect the most significant column address).
The Read A and Read B commands act as point-
ers to the main memory area. Their use depends
on the bus width of the device. In x16 devices the Read A command (00h)
sets the pointer to Area A (the whole of the
main area) that is Words 0 to 255. In x8 devices the Read A command (00h) sets
the pointer to Area A (the first half of the main
area) that is Bytes 0 to 255, and the Read B
command (01h) sets the pointer to Area B (the
second half of the main area) that is Bytes 256
to 511.
In both the x8 and x16 devices the Read C com-
mand (50h), acts as a pointer to Area C (the spare
memory area) that is Bytes 512 to 527 or Words
256 to 263.
Once the Read A and Read C commands have
been issued the pointer remains in the respective
areas until another pointer code is issued. Howev-
er, the Read B command is effective for only one
operation, once an operation has been executed
in Area B the pointer returns automatically to Area
The pointer operations can also be used before a
program operation, that is the appropriate code
(00h, 01h or 50h) can be issued before the pro-
gram command 80h is issued (see Figure 12.).
Figure 11. Pointer Operations
21/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 12. Pointer Operations for Programming
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Read Memory ArrayEach operation to read the memory area starts
with a pointer operation as shown in the Pointer
Operations section. Once the area (main or spare)
has been selected using the Read A, Read B or
Read C commands four bus cycles (for 512Mb
and 1Gb devices) or three bus cycles (for 128Mb
and 256Mb devices) are required to input the ad-
dress (refer to Table 6.) of the data to be read.
The device defaults to Read A mode after power-
up or a Reset operation.
When reading the spare area addresses: A0 to A3 (x8 devices) A0 to A2 (x16 devices)
are used to set the start address of the spare area
while addresses: A4 to A7 (x8 devices) A3 to A7 (x16 devices)
are ignored.
Once the Read A or Read C commands have
been issued they do not need to be reissued for
subsequent read operations as the pointer re-
mains in the respective area. However, the Read
B command is effective for only one operation,
once an operation has been executed in Area B
the pointer returns automatically to Area A and so
another Read B command is required to start an-
other read operation in Area B.
Once a read command is issued three types of op-
erations are available: Random Read, Page Read
and Sequential Row Read.
Random Read. Each time the command is is-
sued the first read is Random Read.
Page Read. After the Random Read access the
page data is transferred to the Page Buffer in a
time of tWHBH (refer to Table 21. for value). Once
the transfer is complete the Ready/Busy signal
goes High. The data can then be read out sequen-
tially (from selected column address to last column
address) by pulsing the Read Enable signal.
Sequential Row Read. After the data in last col-
umn of the page is output, if the Read Enable sig-
nal is pulsed and Chip Enable remains Low then
the next page is automatically loaded into the
Page Buffer and the read operation continues. A
Sequential Row Read operation can only be used
to read within a block. If the block changes a new
read command must be issued.
Refer to Figure 15. and Figure 16. for details of Se-
quential Row Read operations.
To terminate a Sequential Row Read operation set
the Chip Enable signal to High for more than tEHEL.
Sequential Row Read is not available when the
Chip Enable Don't Care option is enabled.
23/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 13. Read (A,B,C) Operations
Figure 14. Read Block DiagramsNote:1. Highest address depends on device density.
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 15. Sequential Row Read Operations
Figure 16. Sequential Row Read Block Diagrams
25/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Page ProgramThe Page Program operation is the standard oper-
ation to program data to the memory array.
The main area of the memory array is pro-
grammed by page, however partial page program-
ming is allowed where any number of bytes (1 to
528) or words (1 to 264) can be programmed.
The maximum number of consecutive partial page
program operations allowed in the same page is
three. After exceeding this a Block Erase com-
mand must be issued before any further program
operations can take place in that page.
Before starting a Page Program operation a Point-
er operation can be performed to point to the area
to be programmed. Refer to the Pointer Opera-
tions section and Figure 12. for details.
Each Page Program operation consists of five
steps (see Figure 17.): one bus cycle is required to setup the Page
Program command four bus cycles are then required to input the
program address (refer to Table 6.) the data is then input (up to 528 Bytes/ 264
Words) and loaded into the Page Buffer one bus cycle is required to issue the confirm
command to start the P/E/R Controller. The P/E/R Controller then programs the data
into the array.
Once the program operation has started the Sta-
tus Register can be read using the Read Status
Register command. During program operations
the Status Register will only flag errors for bits set
to '1' that have not been successfully programmed
to '0'.
During the program operation, only the Read Sta-
tus Register and Reset commands will be accept-
ed, all other commands will be ignored.
Once the program operation has completed the P/
E/R Controller bit SR6 is set to ‘1’ and the Ready/
Busy signal goes High.
The device remains in Read Status Register mode
until another valid command is written to the Com-
mand Interface.
Figure 17. Page Program OperationNote: Before starting a Page Program operation a Pointer operation can be performed. Refer to Pointer Operations section for details.
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Copy Back ProgramThe Copy Back Program operation is used to copy
the data stored in one page and reprogram it in an-
other page.
The Copy Back Program operation does not re-
quire external memory and so the operation is
faster and more efficient because the reading and
loading cycles are not required. The operation is
particularly useful when a portion of a block is up-
dated and the rest of the block needs to be copied
to the newly assigned block.
If the Copy Back Program operation fails an error
is signalled in the Status Register. However as the
standard external ECC cannot be used with the
Copy Back operation bit error due to charge loss
cannot be detected. For this reason it is recom-
mended to limit the number of Copy Back opera-
tions on the same data and or to improve the
performance of the ECC.
The Copy Back Program operation requires three
steps: The source page must be read using the Read
A command (one bus write cycle to setup the
command and then 4 bus write cycles to input
the source page address). This operation
copies all 264 Words/ 528 Bytes from the page
into the Page Buffer. When the device returns to the ready state
(Ready/Busy High), the second bus write
cycle of the command is given with the 4 bus
cycles to input the target page address. Refer
to Table 10. for the addresses that must be the
same for the Source and Target pages. Then the confirm command is issued to start
the P/E/R Controller.
After a Copy Back Program operation, a partial-
page program is not allowed in the target page un-
til the block has been erased.
See Figure 18. for an example of the Copy Back
operation.
Table 10. Copy Back Program AddressesNote:1. DD = Dual Die.
Figure 18. Copy Back Operation
27/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Block EraseErase operations are done one block at a time. An
erase operation sets all of the bits in the ad-
dressed block to ‘1’. All previous data in the block
is lost.
An erase operation consists of three steps (refer to
Figure 19.): One bus cycle is required to setup the Block
Erase command. Only three bus cycles for 512Mb and 1Gb
devices, or two for 128Mb and 256Mb devices
are required to input the block address. The
first cycle (A0 to A7) is not required as only
addresses A14 to A26 (highest address
depends on device density) are valid, A9 to
A13 are ignored. In the last address cycle I/O2
to I/O7 must be set to VIL. One bus cycle is required to issue the confirm
command to start the P/E/R Controller.
Once the erase operation has completed the Sta-
tus Register can be checked for errors.
Figure 19. Block Erase Operation
ResetThe Reset command is used to reset the Com-
mand Interface and Status Register. If the Reset
command is issued during any operation, the op-
eration will be aborted. If it was a program or erase
operation that was aborted, the contents of the
memory locations being modified will no longer be
valid as the data will be partially programmed or
erased.
If the device has already been reset then the new
Reset command will not be accepted.
The Ready/Busy signal goes Low for tBLBH4 after
the Reset command is issued. The value of tBLBH4
depends on the operation that the device was per-
forming when the command was issued, refer to
Table 21. for the values.
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Read Status RegisterThe device contains a Status Register which pro-
vides information on the current or previous Pro-
gram or Erase operation. The various bits in the
Status Register convey information and errors on
the operation.
The Status Register is read by issuing the Read
Status Register command. The Status Register in-
formation is present on the output data bus (I/O0-
I/O7) on the falling edge of Chip Enable or Read
Enable, whichever occurs last. When several
memories are connected in a system, the use of
Chip Enable and Read Enable signals allows the
system to poll each device separately, even when
the Ready/Busy pins are common-wired. It is not
necessary to toggle the Chip Enable or Read En-
able signals to update the contents of the Status
Register.
After the Read Status Register command has
been issued, the device remains in Read Status
Register mode until another command is issued.
Therefore if a Read Status Register command is
issued during a Random Read cycle a new read
command must be issued to continue with a Page
Read or Sequential Row Read operation.
The Status Register bits are summarized in Table
11., Status Register Bits. Refer to Table 11. in
conjunction with the following text descriptions.
Write Protection Bit (SR7). The Write Protection
bit can be used to identify if the device is protected
or not. If the Write Protection bit is set to ‘1’ the de-
vice is not protected and program or erase opera-
tions are allowed. If the Write Protection bit is set
to ‘0’ the device is protected and program or erase
operations are not allowed.
P/E/R Controller Bit (SR6). The Program/Erase/
Read Controller bit indicates whether the P/E/R
Controller is active or inactive. When the P/E/R
Controller bit is set to ‘0’, the P/E/R Controller is
active (device is busy); when the bit is set to ‘1’, the
P/E/R Controller is inactive (device is ready).
Error Bit (SR0). The Error bit is used to identify if
any errors have been detected by the P/E/R Con-
troller. The Error Bit is set to ’1’ when a program or
erase operation has failed to write the correct data
to the memory. If the Error Bit is set to ‘0’ the oper-
ation has completed successfully.
SR5, SR4, SR3, SR2 and SR1 are Reserved.
29/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 11. Status Register Bits
Read Electronic SignatureThe device contains a Manufacturer Code and De-
vice Code. To read these codes two steps are re-
quired: first use one Bus Write cycle to issue the Read
Electronic Signature command (90h) then perform two Bus Read operations – the
first will read the Manufacturer Code and the
second, the Device Code. Further Bus Read
operations will be ignored.
Refer to Table 12., Electronic Signature, for infor-
mation on the addresses.
Table 12. Electronic Signature
