N74F573D ,Octal transparent latch (3-State)FEATURESbroadside pinout configuration to facilitate PC board layout and• 74F573 is broadside pinou ..
N74F573D ,Octal transparent latch (3-State)PIN CONFIGURATION – 74F573
N74F573D ,Octal transparent latch (3-State)INTEGRATED CIRCUITS74F573Octal transparent latch (3-State)74F574Octal transparent latch (3-State)Pr ..
N74F574D ,Octal D Flip-Flop (3-State)INTEGRATED CIRCUITS74F573Octal transparent latch (3-State)74F574Octal transparent latch (3-State)Pr ..
N74F597N ,8-bit shift register with input storage registers
N74F646D ,Octal transceiver/register, non-inverting 3-State
NFM18PS105R0J3D , EMIFIL (Capacitor type) Single Circuit Type for Large Current
NFM18PS474R0J3D , EMIFIL (Capacitor type) Single Circuit Type for Large Current
NFM18PS474R0J3D , EMIFIL (Capacitor type) Single Circuit Type for Large Current
NFM21CC102R1H3D , EMIFIL (Capacitor type) Single Circuit Type for Signal Lines NFM21C Series (0805 Size)
NFM21CC102R1H3D , EMIFIL (Capacitor type) Single Circuit Type for Signal Lines NFM21C Series (0805 Size)
NFM21CC221R1H3D , EMIFIL (Capacitor type) Single Circuit Type for Signal Lines NFM21C Series (0805 Size)
N74F573D-N74F574D
Octal transparent latch 3-State
Product specification
IC15 Data Handbook
1989 Oct 16
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop74F573 Octal Transparent Latch (3-State)
74F574 Octal D Flip-Flop (3-State)
FEATURES 74F573 is broadside pinout version of 74F373 74F574 is broadside pinout version of 74F374 Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors Useful as an Input or Output port for Microprocessors 3-State Outputs for Bus interfacing Common Output Enable 74F563 and 74F564 are inverting version of 74F573 and 74F574
respectively 3-State Outputs glitch free during power-up and power-down These are High-Speed replacements for N8TS805 and N8TS806
DESCRIPTIONThe 74F573 is an octal transparent latch coupled to eight 3-State
output buffers. The two sections of the device are controlled
independently by Enable (E) and Output Enable (OE) control gates.
The 74F573 is functionally identical to the 74F373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
Enable (E) input is High. The latch remains transparent to the data
input while E is High and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independent to the latch operation. When OE is Low, the latched or
transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
The 74F574 is functionally identical to the 74F374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocesors.
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE) control gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independently of the latch operation. When OE is Low, the latched
or transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
ORDERING INFORMATION
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
NOTE: One (1.0) FAST Unit Load is defined as: 20μA in the High state and 0.6mA in the Low state.
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
PIN CONFIGURATION – 74F573
PIN CONFIGURATION – 74F574
LOGIC SYMBOL – 74F573
LOGIC SYMBOL – 74F574
LOGIC SYMBOL (IEEE/IEC) – 74F573
LOGIC SYMBOL (IEEE/IEC) – 74F574
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
LOGIC DIAGRAM – 74F573
FUNCTION TABLE – 74F573= High voltage level= High voltage level one setup time prior to the High-to-Low E transition= Low voltage level= Low voltage level one setup time prior to the High-to-Low E transition
NC= No change= Don’t care= High impedance “off” state= High-to-Low E transition
LOGIC DIAGRAM – 74F574
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
FUNCTION TABLE – 74F574= High voltage level= High voltage level one setup time prior to the Low-to-High clock transition= Low voltage level= Low voltage level one setup time prior to the Low-to-High clock transition
NC= No change= Don’t care= High impedance “off” state= Low-to-High clock transition= Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
DC ELECTRICAL CHARACTERISTICS(Over recommended operating free-air temperature range unless otherwise noted.)
NOTES: For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. All typical values are at VCC = 5V, Tamb = 25°C. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
Philips Semiconductors Product specification
74F573/74F574Latch/flip-flop
AC ELECTRICAL CHARACTERISTICS
AC SETUP REQUIREMENTS
