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N74F5074D-N74F5074N
Synchronizing dual D-type flip-flop/clock driver
Product specification
IC15 Data Handbook
1990 Sep 14
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
FEATURES Metastable immune characteristics Output skew guaranteed less than 1.5ns High source current (IOH = 15mA) ideal for clock driver
applications Pin out compatible with 74F74 74F50728 for synchronizing cascaded D–type flip–flop See 74F50729 for synchronizing dual D–type flip–flop with
edge–triggered set and reset See 74F50109 for synchronizing dual J–K positive
edge–triggered flip–flop Industrial temperature range available (–40°C to +85°C)
ORDERING INFORMATION
INPUT AND OUTPUT LOADING
AND FAN OUT TABLE
NOTE: One (1.0) FAST unit load is defined as: 20μA in the highstate and 0.6mA in the low state.
PIN CONFIGURATION
IEC/IEEE SYMBOL
LOGIC SYMBOL
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
LOGIC DIAGRAM
DESCRIPTIONThe 74F5074 is a dual positive edge–triggered D–type featuring
individual data, clock, set and reset inputs; also true and
complementary outputs.
Set (SDn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. Data must be stable
just one setup time prior to the low–to–high transition of the clock for
guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive–going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output.
The 74F5074 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F5074
are: τ ≅ 135ps and To ≅ 9.8 X 106 sec where τ represents a
function of the rate at which a latch in a metastable state resolves
that condition and T0 represents a function of the measurement of
the propensity of a latch to enter a metastable state.
Metastable Immune CharacteristicsPhilips Semiconductor uses the term ’metastable immune’ to
describe characteristics of some of the products in its family.
Specifically the 74F50XXX family presently consist of 4 products
which will not glitch or display an output anomaly under any
circumstances including setup and hold time violations. This claim is
easily verified on the 74F5074. By running two independent signal
generators (see Fig. 1) at nearly the same frequency (in this case
10MHz clock and 10.02 MHz data) the device–under–test can be
often be driven into a metastable state. If the Q output is then used
to trigger a digital scope set to infinite persistence the Q output will
build a waveform. An experiment was run by continuously operating
the devices in the region where metastability will occur.
When the device–under–test is a 74F74 (which was not designed
with metastable immune characteristics) the waveform will appear
as in Fig. 2.
Figure 2 shows clearly that the Q output can vary in time with
respect to the Q trigger point. This also implies that the Q or Q
output waveshapes may be distorted. This can be verified on an
analog scope with a charge plate CRT. Perhaps of even greater
interest are the dots running along the 3.5V volt line in the upper
right hand quadrant. These show that the Q output did not change
state even though the Q output glitched to at least 1.5 volts, the
trigger point of the scope.
When the device–under–test is a metastable immune part, such as
the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q
output will appear as in Fig. 3. The 74F5074 Q output will not vary
with respect to the Q trigger point even when the a part is driven into
a metastable state. Any tendency towards internal metastability is
resolved by Philips Semiconductor patented circuitry. If a metastable
event occurs within the flop the only outward manifestation of the
event will be an increased clock–to–Q/Q propagation delay. This
propagation delay is, of course, a function of the metastability
characteristics of the part defined by τ and T0.
The metastability characteristics of the 74F5074 and related part
types represent state–of–the–art TTL technology.
After determining the T0 and t of the flop, calculating the mean time
between failures (MTBF) is simple. Suppose a designer wants to
use the 74F5074 for synchronizing asynchronous data that is
arriving at 10MHz (as measured by a frequency counter), has a
clock frequency of 50MHz, and has decided that he would like to
sample the output of the 74F5074 10 nanoseconds after the clock
edge. He simply plugs his number into the equation below:
MTBF = e(t’/t) / TofCfI
In this formula, fC is the frequency of the clock, fI is the average
input event frequency, and t’ is the time after the clock pulse that the
output is sampled (t’ < h, h being the normal propagation delay). In
this situation the fI will be twice the data frequency of 20 MHz
because input events consist of both of low and high transitions.
Multiplying fI by fC gives an answer of 1015 Hz2 . From Fig. 4 it is
clear that the MTBF is greater than 1010 seconds. Using the above
formula the actual MTBF is 1.51 X 1010 seconds or about 480 years.
Figure 1. Test Set-up
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
COMPARISON OF METASTABLE IMMUNE AND NON–IMMUNE CHARACTERISTICS
Figure 2. 74F74 Q Output triggered by Q output, set-up and hold times violated
Figure 3. 74F74 Q Output triggered by Q output, set-up and hold times violated
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’
NOTE: VCC = 5V, Tamb = 25°C, τ =135ps, To = 9.8 X 106 sec
Figure 4.
TYPICAL VALUES FOR τ AND T0 AT VARIOUS VCC S AND TEMPERATURES
FUNCTION TABLE
NOTES:= High voltage level= High voltage level one setup time prior to low–to–high clock transition= Low voltage level = Low voltage level one setup time prior to low–to–high clock transition
NC= No change from the previous setup= Don’t care
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
ABSOLUTE MAXIMUM RATINGS(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS(Over recommended operating free-air temperature range unless otherwise noted.)
NOTES: For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. All typical values are at VCC = 5V, Tamb = 25°C.
