N74F299D ,8-bit universal shift/storage register 3-StatePIN CONFIGURATION• Common parallel I/O for reduced pin countS0 1 20 VCC• Additional serial inputs a ..
N74F3037D ,Quad 2-input NAND 30ohm driverFEATURES transmission line effects of PC boards which appear whenfast edge rates are used.• 30Ω lin ..
N74F3037D ,Quad 2-input NAND 30ohm driverINTEGRATED CIRCUITS74F3037Quad 2-input NAND 30Ω driverProduct specification 1990 Feb 09IC15 Data Ha ..
N74F3037D ,Quad 2-input NAND 30ohm driverFEATURES transmission line effects of PC boards which appear whenfast edge rates are used.• 30Ω lin ..
N74F30D ,8-input NAND gatePIN CONFIGURATIONTYPE TYPICAL TYPICALPROPAGATION SUPPLY CURRENTDELAY (TOTAL) Da 1 14 VCCDb 2 13 NC7 ..
N74F32D ,Quad 2-input OR gatePIN CONFIGURATION• Industrial temperature range available (–40°C to +85°C)D0a 1 14VCCD0b 2 13 D3bTY ..
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NFE61PT101Z1H9L , EMIFIL (LC Combined) Feed through Type
NFE61PT102E1H9L , EMIFIL (LC Combined) Feed through Type
NFE61PT102E1H9L , EMIFIL (LC Combined) Feed through Type
NFE61PT181B1H9L , EMIFIL (LC Combined) Feed through Type
N74F299D
8-bit universal shift/storage register 3-State
Product specification
IC15 Data Handbook
1990 Mar 01
Philips Semiconductors Product specification
74F2998-bit universal shift/storage register (3-State)
FEATURES Common parallel I/O for reduced pin count Additional serial inputs and outputs for expansion Four operating modes: Shift left, shift right, load and store 3-State outputs for bus-oriented applications
DESCRIPTIONThe 74F299 is an 8-bit universal shift/storage register with 3-State
outputs. Four modes of operation are possible: Hold (store), shift
left, shift right and parallel load. The parallel load inputs and flip-flop
outputs are multiplexed to reduce the total number of package pins.
Additional outputs are provided for flip-flops Q0 and Q7 to allow
easy serial cascading. A separate active-Low Master Reset is used
to reset the register.
The 74F299 contains eight edge-triggered D-type flip-flops and the
interstage logic necessary to perform synchronous shift left, shift
right, parallel load and hold operations. The type of operation is
determined by S0 and S1, as shown in the Function Table. All
flip-flop outputs are brought out through 3-State buffers to separate
I/O pins that also serve as data inputs in the parallel load mode.
Q0 and Q7 are also brought out on other pins for expansion in serial
shifting of longer words.
A Low signal on MR overrides the Select and CP inputs and resets
the flip-flops. All other state changes are initiated by the rising edge
of the clock. Inputs can change when the clock is in either state
provided only that the recommended setup and hold times, relative
to the rising edge of clock are observed.
A High signal on either OE0 or OE1 disables the 3-State buffers and
puts the I/O pins in the high impedance state. In this condition the
shift, hold, load and reset operations can still occur. The 3-State
buffers are also disabled by High signals on both S0 and S1 in
preparation for a parallel load operation.
PIN CONFIGURATION
ORDERING INFORMATION
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20μA in the High State and 0.6mA in the Low state.
Philips Semiconductors Product specification
74F2998-bit universal shift/storage register (3-State)
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
FUNCTION TABLE= High voltage level= Low voltage level= Don’t care= Low-to-High clock transition
Philips Semiconductors Product specification
74F2998-bit universal shift/storage register (3-State)
LOGIC DIAGRAM
Philips Semiconductors Product specification
74F2998-bit universal shift/storage register (3-State)
ABSOLUTE MAXIMUM RATINGS(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product specification
74F2998-bit universal shift/storage register (3-State)
DC ELECTRICAL CHARACTERISTICS(Over recommended operating free-air temperature range unless otherwise noted.)
NOTES: For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. All typical values are at VCC = 5V, Tamb = 25°C. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
Philips Semiconductors Product specification
74F2998-bit universal shift/storage register (3-State)
AC ELECTRICAL CHARACTERISTICS
AC SETUP REQUIREMENTS
