N74F273AD ,Octal D flip-flopapplications where the true output only is required and the CP and(20μA in Low and High states)MR ..
N74F273AD ,Octal D flip-flopINTEGRATED CIRCUITS74F273AOctal D flip-flopProduct specification 1996 Mar 12IC15 Data Handbook ..
N74F273AN ,74F273A; Octal D flip-flopPIN CONFIGURATION LOGIC SYMBOLMR 1 20 VCC3 4 7 8 13 14 17 18Q0 2 19 Q7D0 3 18 D7D0 D1 D2 D3 D4 D5 D ..
N74F27D ,Triple 3-input NOR gatePIN CONFIGURATION• Industrial temperature range available (–40°C to +85°C)D0a 1 14 VCCD0b 2 13 D0cT ..
N74F283D ,4-bit binary full adder with fast carry
N74F299D ,8-bit universal shift/storage register 3-StatePIN CONFIGURATION• Common parallel I/O for reduced pin countS0 1 20 VCC• Additional serial inputs a ..
NFE31PT220R1E9 , SMD/BLOCK Type EMI Suppression Filters
NFE31PT220R1E9L , Chip EMIFILr LC Combined Type
NFE31PT220R1E9L , Chip EMIFILr LC Combined Type
NFE31PT221D1E9L , Chip EMIFILr LC Combined Type
NFE31PT221D1E9L , Chip EMIFILr LC Combined Type
NFE31PT222Z1E9 , On-Board Type (DC) EMI Suppression Filters
N74F273AD-N74F273AN
74F273A; Octal D flip-flop
Product specification
IC15 Data Handbook
1996 Mar 12
Philips Semiconductors Product specification
74F273AOctal D flip–flop
FEATURES High impedance inputs for reduced loading
(20μA in Low and High states) Ideal buffer for MOS microprocessor or memory Eight edge–triggered D–type flip–flops Buffered common clock Buffered asynchronous Master Reset See 74F377A for clock enable version See 74F373 for transparent latch version See 74F374 for 3–State version
DESCRIPTIONThe 74F273 has eight edge–triggered D–type flip–flops with
individual D inputs and Q outputs. The common buffered Clock (CP)
and Master Reset (MR) inputs load and reset (clear) all flip–flops
simultaneously.
The register is fully edge–triggered. The state of each D input, one
setup time before the Low–to–High clock transition, is transferred to
the corresponding flip–flop’s Q output.
All outputs will be forced Low independently of Clock or Data inputs
by a Low voltage level on the MR input. The device is useful for
applications where the true output only is required and the CP and
MR are common to all elements.
ORDERING INFORMATION
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PIN CONFIGURATION
LOGIC SYMBOL
Philips Semiconductors Product specification
74F273AOctal D flip–flop
LOGIC SYMBOL (IEEE/IEC)
LOGIC DIAGRAM
FUNCTION TABLE= High voltage level= High voltage level one set–up time prior to the Low–to–High clock transition= Low voltage level = Low voltage level one set–up time prior to the Low–to–High clock transition= Don’t care= Low–to–High clock transition
Philips Semiconductors Product specification
74F273AOctal D flip–flop
ABSOLUTE MAXIMUM RATINGS(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product specification
74F273AOctal D flip–flop
DC ELECTRICAL CHARACTERISTICS(Over recommended operating free-air temperature range unless otherwise noted.)
NOTES: For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. All typical values are at VCC = 5V, Tamb = 25°C. To reduce the effect of external noise during test. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
AC CHARACTERISTICS FOR ’F273A
Philips Semiconductors Product specification
74F273AOctal D flip–flop
AC SETUP REQUIREMENTS FOR ’F273A
AC WAVEFORMS
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
Waveform 2. Master Reset Pulse Width, Master Reset to Output
Delay and Master Reset to Clock Recovery Time
Waveform 3. Data Setup and Hold Times
NOTE: For all waveforms, VM = 1.5V.The shaded areas indicate when the input is permitted to change for predictable output
performance.
