N74F194D ,4-bit bidirectional universal shift registerfeatures which increase theTYPICALrange of application. The synchronous operation of the device isT ..
N74F194D ,4-bit bidirectional universal shift register
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N74F194D
4-bit bidirectional universal shift register
Product specification
IC15 Data Handbook
1989 Apr 04
Philips Semiconductors Product specification
74F1944-bit bidirectional universal shift register
FEATURES Shift right and shift left capability Synchronous parallel and serial data transfer Easily expanded for both serial and parallel operation Asynchronous Master Reset Hold (do nothing) mode
DESCRIPTIONThe functional characteristics of the 74F194 4-Bit Bidirectional Shift
Register are indicated in the Logic Diagram and Function Table. The
register is fully synchronous, with all operations taking place in less
than 9ns (typical) for 74F, making the device especially useful for
implementing very high speed CPUs, or for memory buffer registers.
The 74F194 design has special logic features which increase the
range of application. The synchronous operation of the device is
determined by two Mode Select inputs, S0 and S1. As shown in the
Mode Select-Function Table, data can be entered and shifted from
left to right (shift right, Q0→Q1, etc.), or right to left (shift left,
Q3→Q2, etc.), or parallel data can be entered, loading all 4 bits of
the register simultaneously. When both S0 and S1 are Low, existing
data is retained in a hold (do nothing) mode. The first and last
stages provide D-type Serial Data inputs (DSR, DSL) to allow
multistage shift right or shift left data transfers without interfering
with parallel load operation. Mode Select and data inputs on the
74F194 are edge-triggered, responding only to the Low-to-High
transition of the Clock (CP). Therefore, the only timing restriction is
that the Mode Select and selected data inputs must be stable one
setup time prior to the Low-to-High transition of the clock pulse.
Signals on the Mode Select, Parallel Data (D0–D3) and Serial Data
(DSR, DSL) can change when the clock is in either state, provided
only the recommended setup and hold times, with respect to the
clock rising edge, are observed. The four Parallel Data inputs
(D0–D3) are D-type inputs. Data appearing on (D0–D3) inputs when
S0 and S1 are High is transferred to the Q0–Q3 outputs
respectively, following the next Low-to-High transition of the clock.
When Low, the asynchronous Master Reset (MR) overrides all other
input conditions and forces the Q outputs Low.
PIN CONFIGURATION
ORDERING INFORMATION
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
NOTE: One (1.0) FAST unit load is defined as: 20μA in the High state and 0.6mA in the Low state.
Philips Semiconductors Product specification
74F1944-bit bidirectional universal shift register
LOGIC SYMBOL
IEC/IEEE SYMBOL
LOGIC DIAGRAM
Philips Semiconductors Product specification
74F1944-bit bidirectional universal shift register
FUNCTION TABLEH = High voltage level
h = High voltage level one setup time prior to Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition.
ABSOLUTE MAXIMUM RATINGS(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product specification
74F1944-bit bidirectional universal shift register
DC ELECTRICAL CHARACTERISTICS
NOTES: For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. All typical values are at VCC = 5V, Tamb = 25°C. Output High state will change to Low stat if an external voltage of less than 0.0V is applied. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last. With all outputs open, Di inputs grounded and a 4.5V applied to S0, S1, MR and the serial inputs, ICC is tested with a momentary ground,
then 4.5V applied to CP.
AC ELECTRICAL CHARACTERISTICS
AC SETUP REQUIREMENTS
Philips Semiconductors Product specification
74F1944-bit bidirectional universal shift register
AC WAVEFORMSFor all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
Waveform 2. Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Clock Recovery Time
Waveform 3. Setup and Hold Times
TIMING DIAGRAMTypical Clear, Load, Shift-Right, Shift-Left and Inhibit Sequence
