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MXD1210CPA-MXD1210CSA-MXD1210CWE-MXD1210ESA-MXD1210EWE
Nonvolatile RAM Controller
& the latest literature: http://,
_______________General DescriptionThe MXD1210 nonvolatile RAM controller is a very low-
power CMOS circuit that converts standard (volatile)
CMOS RAM into nonvolatile memory. It also continually
monitors the power supply to provide RAM write protec-
tion when power to the RAM is in a marginal (out-of-
tolerance) condition. When the power supply begins to
fail, the RAM is write protected, and the device switch-
es to battery-backup mode.
ApplicationsµP Systems
Computers
Embedded Systems
____________________________FeaturesBattery BackupMemory Write Protection230µA Operating-Mode Quiescent Current2nA Backup-Mode Quiescent CurrentBattery Freshness SealOptional Redundant BatteryLow Forward-Voltage Drop on VCCSupply Switch5% or 10% Power-Fail Detection OptionsTests Battery Condition During Power-Up8-Pin SO Available
______________Ordering Information*Contact factory for dice specifications.
MXD1210
Nonvolatile RAM Controller
________________________________________________________________Maxim Integrated Products1
__________Typical Operating Circuit19-0154; Rev 1; 3/96
_________________Pin Configurations
MXD1210
Nonvolatile RAM Controller
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(TA= TMINto TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS(VCCI= +4.75V to +5.5V, TOL = GND; or VCCI= +4.5V to +5.5V, TOL = VCCO; TA= TMINto TMAX; unless otherwise noted.)
VCCIto GND................................................................-0.3V, +7V
VBATT1 to GND..........................................................-0.3V, +7V
VBATT2 to GND.......................................................... -0.3V, +7V
VCCOto GND..................................................... -0.3V, VS+ 0.3V
(VS= greater of VCCI, VBATT1, VBATT2)
Digital Input and Output Voltages to GND............. 0.3V, VCCI+ 0.3V
Continuous Power Dissipation (TA= +70°C)
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C)....727mW
8-Pin SO (derate 5.88mW/°C above +70°C).................471mW
16-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW
8-Pin CERDIP (derate 8.00mW/°C above +70°C).........640mW
Operating Temperature Ranges
MXD1210C_ _..................................................... 0°C to +70°C
MXD1210E_ _.................................................. -40°C to +85°C
MXD1210MJA................................................ -55°C to +125°C
Storage Temperature Range ........................... -65°C to +150°C
Lead Temperature (soldering, 10sec)............................ +300°C
Nonvolatile RAM Controller
ELECTRICAL CHARACTERISTICS(VCCI< VBATT; positive edge rate at VBATT1, VBATT2 > 0.1V/ms, TA= TMINto TMAX; unless otherwise noted.)
MXD1210
ELECTRICAL CHARACTERISTICS(TA= TMINto TMAX, unless otherwise noted.)
_______________________________________________________________________________________3CCPOWER TIMING CHARACTERISTICS(VCCI = +4.75V to +5.5V, TOL = GND; or VCCI= +4.5V to +5.5V, TOL = VCCO; TA= TMINto TMAX; unless otherwise noted.)
TIMING CHARACTERISTICS(VCCI< +4.75V to +5.5V, TOL = GND; or VCCI< +4.5V , TOL = VCCO; TA= TMINto TMAX; unless otherwise noted.)
Note 1:Only one battery input is required. Unused battery inputs must be grounded.
Note 2:ICCO1is the maximum average load current the MXD1210 can supply to the memories.
Note 3:ICCO2is the maximum average load current the MXD1210 can supply to the memories in battery-backup mode.
Note 4:CEOcan sustain leakage current only in battery-backup mode.
Note 5:Guaranteed by design.
Note 6:tCEmax must be met to ensure data integrity on power loss.
MXD1210
Nonvolatile RAM Controller_______________________________________________________________________________________
______________________________________________________________Pin DescriptionFigure 1. Block Diagram
______________Detailed Description
Main FunctionsThe MXD1210 executes five main functions to perform
reliable RAM operation and battery backup (see
Typical Operating Circuitand Figure 1):
1. RAM Power-Supply Switch: The switch directs
power to the RAM from the incoming supply or
from the selected battery, whichever is at the
greater voltage. The switch control uses the same
criterion to direct power to MXD1210 internal
circuitry.
2. Power-Failure Detection: The write-protection func-
tion is enabled when a power failure is detected.
The power-failure detection range depends on the
state of the TOL pin as follows:
Power-failure detection is independent of the battery-
backup function and precedes it sequentially as the
power-supply voltage drops during a typical power
failure.
3. Write Protection: This holds the chip-enable output
(CEO) to within 0.2V of VCCIor of the selected bat-
tery, whichever is greater. If the chip-enable input
(CE)is low (active) when power failure is detected,
then CEOis held low until CEis brought high, at
which time CEOis gated high for the duration of
the power failure. The preceding sequence com-
pletes the current RD/WR cycle, preventing data
corruption if the RAM access is a WR cycle.
4. Battery Redundancy: A second battery is optional.
When two batteries are connected, the stronger
battery is selected to provide RAM backup and to
power the MXD1210. The battery-selection circuitry
remains active while in the battery-backup mode,
selecting the stronger battery and isolating the
weaker one. The battery-selection activity is trans-
parent to the user and the system. If only one bat-
tery is connected, the second battery input should
be grounded.
5. Battery-Status Warning: This notifies the system
when the stronger of the two batteries measures 2.0V. Each time the MXD1210 is repowered
(VCCI> VCCTP) after detecting a power failure, the
battery voltage is measured. If the battery in use is
low, following the MXD1210 recovery period, the
device issues a warning to the system by inhibit-
ing the second memory cycle. The sequence is as
follows:
First access: read memory location n, loc(n) = x
Second access: write memory location n,
loc (n) = complement (x)
Third access: read memory location n, loc (n) =
If the third access (read) is complement (x), then the
battery is good; otherwise, the battery is not good.
Return to loc(n) = x following the test sequence.
Freshness-Seal ModeThe freshness-seal mode relates to battery longevity
during storage rather than directly to battery backup.
This mode is activated when the first battery is connect-
ed, and is defeated when the voltage at VCCIfirst
exceeds VCCTP. In the freshness-seal mode, both bat-
teries are isolated from the system; that is, no current is
drained from either battery, and the RAM is not pow-
ered by either battery. This means that batteries can be
installed and the system can be held in inventory with-
out battery discharge. The positive edge rate at
VBATT1 and VBATT2 should exceed 0.1V/ms. The bat-
teries will maintain their full shelf-life while installed in
the system.
Battery BackupThe Typical Operating Circuitshows the MXD1210 con-
nected in order to write protect the RAM when VCCis
less than 4.75V, and to provide battery backup to the
supply.
MXD1210
Nonvolatile RAM Controller
_______________________________________________________________________________________5
MXD1210
Nonvolatile RAM Controller_______________________________________________________________________________________Figure 2. Power-Up Timing DiagramFigure 3. Power-Down Timing Diagram
