MX7837BN+ ,Complete, Dual, 12-Bit Multiplying DAC with 8-Bit Bus InterfaceApplicationsMX7837JN0°C to +70°C 24 Narrow Plastic DIP ±1Small Component-Count Analog SystemsMX7837 ..
MX7837JR ,Complete, dual, 12-bit multiplying DAC. 8-bit + 4-bit interface. Error (LSB) +-1ApplicationsMX7837JN0°C to +70°C 24 Narrow Plastic DIP ±1Small Component-Count Analog SystemsMX7837 ..
MX7837KN ,Complete, dual, 12-bit multiplying DAC. 8-bit + 4-bit interface. Error (LSB) +-1/2FeaturesThe MX7837/MX7847 are dual, 12-bit, multiplying, volt-' Two 12-Bit Multiplying DACs with Bu ..
MX7837KN ,Complete, dual, 12-bit multiplying DAC. 8-bit + 4-bit interface. Error (LSB) +-1/2ApplicationsMSB LSB_________________Pin ConfigurationsINPUT INPUTLATCHLATCH48DAC LATCH ATOP VIEWRFB ..
MX7837KR ,Complete, dual, 12-bit multiplying DAC. 8-bit + 4-bit interface. Error (LSB) +-1/2ELECTRICAL CHARACTERISTICS(V = 11.4V to 16.5V, V = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, V = ..
MX7837KR+ ,Complete, Dual, 12-Bit Multiplying DAC with 8-Bit Bus InterfaceMX7837/MX784719-0158; Rev 0; 7/93Complete, Dual, 12-Bit Multiplying DACs_______________
NDS8936 ,Dual N-Channel Enhancement Mode Field Effect TransistorJuly 1996 N NDS8936Dual N-Channel Enhancement M ode Field Effect Transistor
NDS8947 ,Dual P-Channel Enhancement Mode Field Effect Transistor
NDS8947 ,Dual P-Channel Enhancement Mode Field Effect Transistor
NDS8947 ,Dual P-Channel Enhancement Mode Field Effect Transistor
NDS8958 ,Dual N & P-Channel Enhancement Mode Field Effect TransistorElectrical Characteristics (T = 25°C unless otherwise noted)ASymbol Parameter Conditions Type Min T ..
NDS8961 ,Dual N-Channel Enhancement Mode Field Effect TransistorFeatures3.1A, 30V. R = 0.1Ω @ V = 10V SO-8 N-Channel enhancement mode power field ..
MX7837BN+-MX7837KR+-MX7847JN+
Complete, Dual, 12-Bit Multiplying DAC with 8-Bit Bus Interface
_______________General DescriptionThe MX7837/MX7847 are dual, 12-bit, multiplying, volt-
age-output digital-to-analog converters (DACs). Each
DAC has an output amplifier and a feedback resistor.
The output amplifier is capable of developing ±10V
across a 2kΩload. The amplifier feedback resistor is
internally connected to VOUTon the MX7847. No exter-
nal trims are required to achieve full 12-bit performance
over the entire operating temperature range.
The MX7847 has a 12-bit parallel data input, whereas
the MX7837 operates with a double-buffered 8-bit-bus
interface that loads data in two write operations. All
logic signals are level triggered and are TTL and CMOS
compatible. Fast timing specifications make these
DACs compatible with most microprocessors.
________________________ApplicationsSmall Component-Count Analog Systems
Digital Offset/Gain Adjustments
Industrial Process Control
Function Generators
Automatic Test Equipment
Automatic Calibration
Machine and Motion Control Systems
Waveform Reconstruction
Synchro Applications
____________________________FeatureTwo 12-Bit Multiplying DACs with Buffered
Voltage OutputSpecified with ±12V or ±15V SuppliesNo External Adjustments RequiredFast Timing Specifications24-Pin DIP and SO Packages12-Bit Parallel Interface (MX7847)
8-Bit + 4-Bit Interface (MX7837)
______________Ordering Information
Ordering Information continued on last page.* Contact factory for availability and processing to MIL-STD-883.
Complete, Dual, 12-Bitultiplying DACs13
DB0/DB8
DB1/DB9
DB2/DB10
DB3/DB11
DB4
DB5
DB6
DB7
LDACRFBB
DGND
VREFB
VOUTB
AGNDB
VSS
VDD
AGNDA
VOUTA
VREFA
RFBA
DIP/SOTOP VIEW
MX7837
MX7847 on last page.
_________________Pin Configurations8
DAC LATCH A
MSB
INPUTLATCH
LSB
INPUT
LATCH
DAC A8
DAC LATCH B
MSBINPUT
LATCH
LSB
INPUTLATCH
DAC B
CONTROL
LOGIC
LDAC
DB7
DB0
VREFB
VREFA
RFBA
VOUTA
AGNDA
RFBB
VOUTB
AGNDB
DGNDVSS
VDD
MX7837
MX7847 on last page.
_________Typical Operating Circuits19-0158; Rev 0; 7/93
PARTTEMP. RANGEPIN-PACKAGE
MX7837JN0°C to +70°C24 Narrow Plastic DIP
MX7837KN0°C to +70°C24 Narrow Plastic DIP
MX7837JR0°C to +70°C24 Wide SO
MX7837KR0°C to +70°C24 Wide SO
MX7837C/D0°C to +70°CDice*
ERROR
(LSB)±1/2
±1/2
Complete, Dual, 12-Bit ultiplying DACs
ABSOLUTE MAXIMUM RATINGSVDDto DGND, AGNDA, AGNDB............................-0.3V to +17V
VSSto DGND, AGNDA, AGNDB (Note 1) ..............+0.3V to -17V
VREFA, VREFBto AGNDA, AGNDB ..(VSS- 0.3V) to (VDD+ 0.3V)
AGNDA, AGNDB to DGND.........................-0.3V to (VDD+ 0.3V)
VOUTA, VOUTBto AGNDA, AGNDB.....(VSS- 0.3V) to (VDD+ 0.3V)
RFBA, RFBBto AGNDA, AGNDB.......(VSS- 0.3V) to (VDD+ 0.3V)
Digital Inputs to DGND...............................-0.3V to (VDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
NarrowPlastic DIP (derate 13.33mW/°C above +70°C)....1067mW
SO (derate 11.76mW/°C above +70°C).........................941mW
Narrow CERDIP (derate 12.50mW/°C above +70°C)..1000mW
Operating Temperature Ranges:
MX78_7J_/K_........................................................0°C to +70°C
MX78_7A_/B_ ..................................................-40°C to +85°C
MX78_7SQ/TQ ...............................................-55°C to +125°C
Storage Temperature Range............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
ELECTRICAL CHARACTERISTICS(VDD= 11.4V to 16.5V, VSS= -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA= VREFB= +10V, RL= 2kΩ, CL= 100pF,
VOUTconnected to RFB(MX7837), TA= TMINto TMAX, unless otherwise noted.) (Note 2)
Note 1:If VSSis open-circuited with VDDand either AGNDapplied, the VSSpin will float positive exceeding the Absolute Maximum Ratings.
If this possibility exists, a Schottky diode connected between VSSand GND ensures the maximum ratings will be observed.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PARAMETERSYMBOLMINTYPMAXUNITSDifferential NonlinearityDNL±1LSB
Relative AccuracyINL±1/2LSBZero-Code Offset Error
ResolutionN12Bits
Loaded with all 0s,
tempco =
±5μV/°C typ
CONDITIONSMX78_7J/A= +25°C
Guaranteed monotonic
MX78_7K/B/T
MX78_7K/B
MX78_7S/T
MX78_7J/A/S
MX78_7K/B/T
MX78_7J/A/S= +25°C
MX78_7J/A/S±7Gain Error
Loaded with all 1s,
tempco = ±2ppm
of FSR/°C typTA= TMINto TMAXMX78_7K/B/T±4
LSB
VREFInput Resistance81013kΩ
VREFA, VREFB Resistance
Matching±0.5±3%
Input High Voltage2.4VInput Low Voltage0.8
Input CurrentDigital inputs at 0V and VDD±1μA
Input Capacitance (Note 4)8pF
DC Output Impedance0.2Ω
Short-Circuit CurrentVOUTconnected to AGND15mA
VINH= TMINto TMAX
VINL
STATIC PERFORMANCE (Note 3)
REFERENCE INPUTS
DIGITAL INPUTS
ANALOG OUTPUTS
Complete, Dual, 12-Bitultiplying DACs
PARAMETERSYMBOLMINTYPMAXUNITSCONDITIONS±0.01
±0.01
±0.01Power-Supply Rejection
±0.01
% per %
Voltage-Output Settling
TimetSSettling time to within ±1/2LSB of final DAC value;
DAC latch alternately loaded will all 0s and all 1s4μs
Slew Rate7V/μs
Digital-to Analog Glitch
ImpulseQDAC latch alternately loaded with 01…11 and
10…0060nV-s
Channel-to-Channel Isolation
(VREFA to VOUTB,
VREFBto VOUTA)
VREF= 20p-p, 10kHz sine wave, Alternate DAC
Latch Loaded with all 0s-95dB
Multiplying Feedthrough
Error-90dB
Unity-Gain Small-Signal
Bandwidth
THDMHz
Full-Power Bandwidth125kHz
Total Harmonic DistortionVREF= 6VRMS, 1kHz, DAC latch loaded with all 1s-88dB
Digital CrosstalkCode transition from all 0s to all 1s; see Typical
Operating Characteristics graphs10nV-s
Output Noise Voltage at
+25°C(0.1Hz to 10Hz)Amplifier noise and Johnson noise of RFB2μVRMS
VDDRangeVDD11.416.5V
Positive Supply CurrentIDD510mAOutput unloaded
Negative Supply CurrentISS46mAOutput unloaded
VSSRangeVSS-11.4-16.5V
VREF= 20Vp-pSine wave, DAC latch loaded with
all 1s
VREF= 100mVp-psine wave, DAC latch loaded
with all 1s
VREF_= 20Vp-p, 10kHz sine wave, latches loaded
with all 0s
VSS= -12V ±5%, VREF= 8.9V
VDD= 12V ±5%, VREF= -8.9V
VSS= -15V ±5%, VREF= 10V
VDD= 15V ±5%, VREF= -10VΔGain/ΔVDD
ΔGain/ΔVSS
ΔGain/ΔVSS
ΔGain/ΔVDD
ELECTRICAL CHARACTERISTICS (continued)(VDD= 11.4V to 16.5V, VSS= -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA= VREFB= +10V, RL= 2kΩ, CL= 100pF,
VOUTconnected to RFB(MX7837), TA= TMINto TMAX, unless otherwise noted.) (Note 1)
Note 2:The analog outputs can swing to within 2.5V of the supply rails. Hence, for good linearity towards full-scale, |VREFA| and |VREFB| must
be at least 2.5V lower than VDDand |VSS|. Tests done with supply voltages below ±12.5V are done with VREFA= VREFB= ±8.9V.
Note 3:Static performance tested at VDD= +15V, VSS= -15V. Performance over supplies guaranteed by PSRR test.
Note 4:Guaranteed by design.
POWER REQUIREMENTS
AC CHARACTERISTICS
Complete, Dual, 12-Bit ultiplying DACs
__________________________________________Typical Operating Characteristics(TA= +25°C, VDD= 15V, VSS= -15V, RL= 2kΩ, CL= 100pF, unless otherwise noted)1k10k
OUTPUT VOLTAGE SWING
vs. RESISTIVE LOADLOAD RESISTANCE (W)
(V
VREF = 20Vp-p at 1kHz100k
NOISE SPECTRAL DENSITYFREQUENCY (Hz)
(n
/ H
1001k10k
VREF = 0V
DAC CODE = 11...111
GAIN = -1
10010k10M
SMALL-SIGNAL FREQUENCY RESPONSEFREQUENCY (Hz)
(d-5
-20100k1M
VREF = 100mVp-p
DAC CODE = 11...111
GAIN = -1
-85100k
MULTIPLYING FEEDTHROUGH ERRORFREQUENCY (Hz)
10k1M
VREFA = 20Vp-p
VREFB = AGNDB
DAC CODE = 00...00
1001k10k
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (BANDWIDTH = 80kHz)FREQUENCY (Hz)
(d
VREF = 6VRMS
DAC CODE = 111...111
10010k100k
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (BANDWIDTH > 500kHz)FREQUENCY (Hz)
(d
VREF = 6VRMS
DAC CODE = 111...111
PARAMETERMX78_7J/K/A/B
MINMAXSYMBOLMX78_7S/T
MINMAXUNITSAddress to WRSetupTimet6MX7837 only1515ns
Address to WRHold Timet7MX7837 only1515ns
LDACPulse Widtht8MX7837 only8080ns
CONDITIONSto WRHold Timeto WRSetup Timet10ns0nsPulse Widtht38080ns
Data to WRSetup Timet48080ns
Data to WRHold Timet51010ns
TIMING CHARACTERISTICS(VDD= 11.4V to 16.5V, VSS= -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, TA= TMINto TMAX, unless otherwise noted.) (Note 5)
Note 5:All input signals are specified with tR= tF≤5ns. Logic swing is 0V to 5V.
Complete, Dual, 12-Bitultiplying DACsAGNDA
A = VOUTA, 50mV/div
TIMEBASE = 2ms/div
VREFA = ±100mV SQUARE WAVE
SMALL-SIGNAL PULSE RESPONSEAGNDA
A = VOUTA, 5V/div
TIMEBASE = 2ms/div
VREFA = ±10V SQUARE WAVE
LARGE-SIGNAL PULSE RESPONSE
______________________________________________________________Pin Description
PIN
MX7837MX7847NAMEFUNCTION–CSChip Select – active-low logic input1CSAChip-Select Input for DAC A – active-low logic inputRFBAAmplifier Feedback Resistor for DAC A2CSBChip-Select Input for DAC B – active-low logic input3VREFAReference Input Voltage for DAC A4VOUTAAnalog Output Voltage from DAC A5AGNDAAnalog Ground for DAC A6VDDPositive Power Supply7VSSNegative Power Supply8AGNDBAnalog Ground for DAC B9VOUTBAnalog Output Voltage from DAC B10VREFBReference Input Voltage for DAC B11DGNDDigital Ground–RFBBAmplifier Feedback Resistor for DAC B12DB11Data Bit 11 (MSB)13WRWrite Input – active-low logic input (MX7837); positive-edge-triggered input used with
CSAandCSB(MX7847)–LDACAsynchronous Load – DAC input, active-low14-24DB10-DB0Data Bit 10 to Data Bit 0 (LSB)–A1Address Input – most significant address input for input latches–A0Address Input – least significant address input for input latches
17-20–DB7-DB4Data Bit 7 to Data Bit 4
21-24–DB3/DB11-
DB0/DB8Data Bit 3 to Data Bit 0 (LSB), or Data Bit 11 (MSB) to Data Bit 8
____________________________Typical Operating Characteristics (continued)(TA= +25°C, VDD= 15V, VSS= -15V, RL= 2kW, CL = 100pF, unless otherwise noted.)
_______________Detailed Description
D/A SectionFigure 1 shows a simplified circuit diagram for one of
the DACs and the output amplifier. Using a segmented
scheme, the two MSBs of the 12-bit data word are
decoded to drive the three switches (A to C). The
remaining 10 bits drive the switches (S0 to S9) in a
standard R-2R ladder.
Each switch (A to C) directs 1/4 of the total reference
current, and the remaining current passes through the
R-2R section.
The output amplifier and feedback resistor convert cur-
rent to voltage as follows: VOUT_= (-D)(VREF_), where D
is the fractional representation of the digital word. (D
can be set from 0 to 4095/4096.)
The output amplifier is capable of developing ±10V
across a 2kΩload. It is internally compensated and
settles to 0.01% FSR (1/2LSB) in less than 4μs. VOUT
on the MX7837 is not internally connected to RFB.
Interface Logic InformationX7847)Figure 2 shows the MX7847 input control logic. The
device contains two independent DACs, each with its
own CSinput and a common WRinput. CSAand WR
control data loading to the DAC A latch, and CSBandcontrol data loading to the DAC B latch. The latch-
es are edge triggered so that input data is latched to
the respective latch on WR's rising edge. The same
data will be latched to both DACs if CSAand CSBare
low and WRis taken high. Table 1 shows the device
control-logic truth table, and Figure 3 shows the write-
cycle timing diagram.
Table 1. MX7847 Truth TableX = Don't Care = Rising Edge Triggered
Interface Logic InformationX7837)The MX7837 input loading structure is configured for
interfacing with 8-bit-wide data-bus microprocessors.
Each DAC has two 12-bit latches: an input latch, and a
DAC latch. Each input latch is subdivided into a least-
significant 8-bit latch and a most-significant 4-bit latch.
The data held in the DAC latches determines the out-
puts. Figure 4 shows the MX7837 input control logic,
and Figure 5 shows the write-cycle timing diagram.
Complete, Dual, 12-Bit ultiplying DACs2R2R2R2R2R2RBAS9S8S0
VREFRRR
R/2
VOUT
AGNDSHOWN FOR ALL 1s ON DAC
DAC A LATCH
DAC B LATCH
CSA
CSB
Figure 1.D/A Simplified Circuit Diagramt1t2t4
VALID DATA
CSA, CSB
DATA
Figure 2.MX7847 Input Control LogicFigure 3.MX7847 Write-Cycle Timing Diagram
CSACSBWR
FunctionX1No Data Transfer1XNo Data Transfer1Data Latched to DAC A0Data Latched to DAC B0Data Latched to Both DACs0Data Latched to DAC A0Data Latched to DAC BData Latched to Both DACs
