MX7575AQ ,CMOS / uP-Compatible / 5s/10s / 8-Bit ADCsELECTRICAL CHARACTERISTICS(V = +5V; V = 1.23V; AGND = DGND = 0V; f = 4MHz external for MX7575; f = ..
MX7575JCWN ,CMOS / uP-Compatible / 5s/10s / 8-Bit ADCsMX7575/MX757619-0876; Rev 1; 5/96CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs_______________
MX7575JCWN ,CMOS / uP-Compatible / 5s/10s / 8-Bit ADCsApplicationsMX7575JP 0°C to +70°C 20 PLCC ±1Digital Signal ProcessingMX7575KP 0°C to +70°C 20 PLCC ..
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MX7575JN ,CMOS / uP-Compatible / 5s/10s / 8-Bit ADCsFeaturesMaxim’s MX7575/MX7576 are high-speed (5µs/10µs),' Fast Conversion Time: 5µs (MX7575)micropr ..
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MX7575AQ-MX7575JCWN-MX7575JN-MX7575JP-MX7575KEWN-MX7575KN-MX7575KP-MX7576AQ-MX7576JN-MX7576JP
CMOS / uP-Compatible / 5s/10s / 8-Bit ADCs
& the latest literature: http://,
_______________General DescriptionMaxim’s MX7575/MX7576 are high-speed (5µs/10µs),
microprocessor (µP) compatible, 8-bit analog-to-digital
converters (ADCs). The MX7575 provides an on-chip
track/hold function that allows full-scale signals up to
50kHz (386mV/µs slew rate) to be acquired and digi-
tized accurately. Both ADCs use a successive-approxi-
mation technique to achieve their fast conversions and
low power dissipation. The MX7575/MX7576 operate
with a +5V supply and a 1.23V external reference. They
accept input voltages ranging from 0V to 2VREF.
The MX7575/MX7576 are easily interfaced to all popu-
lar 8-bit µPs through standard CSand RDcontrol sig-
nals. These signals control conversion start and data
access. A BUSYsignal indicates the beginning and
end of a conversion. Since all the data outputs are
latched and three-state buffered, the MX7575/MX7576
can be directly tied to a µP data bus or system l/O port.
Maxim also makes the MAX165, a plug-in replacement
for the MX7575 with an internal 1.23V reference. For
applications that require a differential analog input and
an internal reference, the MAX166is recommended.
________________________ApplicationsDigital Signal Processing
High-Speed Data Acquisition
Telecommunications
Audio Systems
High-Speed Servo Loops
Low-Power Data Loggers
____________________________FeaturesFast Conversion Time:5µs (MX7575)
10µs (MX7576)Built-In Track/Hold Function (MX7575)Low Total Unadjusted Error (±1LSB max)50kHz Full-Power Signal Bandwidth (MX7575)Single +5V Supply Operation8-Bit µP Interface100ns Data-Access TimeLow Power: 15mWSmall-Footprint Packages
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
________________________________________________________________Maxim Integrated Products119-0876; Rev 1; 5/96
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +5V; VREF= 1.23V; AGND = DGND = 0V; fCLK= 4MHz external for MX7575; fCLK= 2MHz external for MX7576;= TMINto TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND...............................................................-0.3V, +7V
VDDto DGND..............................................................-0.3V, +7V
AGND to DGND...............................................-0.3V, VDD+ 0.3V
Digital Input Voltage to DGND
(CS, RD, TP, MODE)......................................-0.3V, VDD+ 0.3V
Digital Output Voltage to DGND
(BUSY, D0–D7)..............................................-0.3V, VDD+ 0.3V
CLK Input Voltage to DGND............................-0.3V, VDD+ 0.3V
REF to AGND...................................................-0.3V, VDD+ 0.3V
AIN to AGND....................................................-0.3V, VDD+ 0.3V
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C)...............889mW
Wide SO (derate 9.52mW/°C above +70°C)..................762mW
CERDIP (derate 10.53mW/°C above +70°C).................842mW
PLCC (derate 10.00mW/°C above +70°C)....................800mW
Operating Temperature Ranges
MX757_J/K............................................................0°C to +70°C
MX757_A/B........................................................-25°C to +85°C
MX757_JE/KE....................................................-40°C to +85°C
MX757_S/T.......................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering,10sec)..............................+300°C
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
_______________________________________________________________________________________3
Note 1:Offset Error is measured with respect to an ideal first-code transition that occurs at 1/2LSB.
Note 2:Sample tested at +25°C to ensure compliance.
Note 3:Accuracy may degrade at conversion times other than those specified.
Note 4:Power-supply current is measured when MX7575/MX7576 are inactive, i.e.:
For MX7575 CS= RD= BUSY= high;
For MX7576 CS= RD= BUSY= MODE = high.
ELECTRICAL CHARACTERISTICS (continued)(VDD= +5V; VREF= 1.23V; AGND = DGND = 0V; fCLK= 4MHz external for MX7575; fCLK= 2MHz external for MX7576;= TMINto TMAX, unless otherwise noted.)
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs_______________________________________________________________________________________
______________________________________________________________Pin Description
TIMING CHARACTERISTICS (Note 5)(VDD= +5V, VREF= 1.23V, AGND = DGND = 0V.)
Note 5:Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with = tf= 20ns (10% to 90% of +5V) and timed from a voltage level of 1.6V.
Note 6:t3and t6are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7:t7is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
Figure 1. Load Circuits for Data-Access Time Test
_______________Detailed Description
Converter Operation The MX7575 and MX7576 use the successive-approxi-
mation technique to convert an unknown analog input
voltage to an 8-bit digital output code (seeFunctional
Diagrams). The MX7575 samples the input voltage on
an internal capacitor once (at the beginning of the con-
version), while the MX7576 samples the input signal
eight times during the conversion (see MX7575
Track/Hold and MX7576 Analog Inputsections). The
internal DAC is initially set to half scale, and the com-
parator determines whether the input signal is larger
than or smaller than half scale. If it is larger than half
scale, the DAC MSB is kept. But if it is smaller, the MSB
is dropped. At the end of each comparison phase, the
SAR (successive-approximation register) stores the
results of the previous decision and determines the
next trial bit. This information is then loaded into the
DAC after each decision. As the conversion proceeds,
the analog input is approximated more closely by com-
paring it to the combination of the previous DAC bits
and a new DAC trial bit. After eight comparison cycles,
the eight bits stored in the SAR are latched into the out-
put latches. At the end of the conversion, the BUSYsig-
nal goes high, and the data in the output latches is
ready for microprocessor (µP) access. Furthermore, the
DAC is reset to half scale in preparation for the next
conversion.
Microprocessor InterfaceThe CSand RDlogic inputs are used to initiate conver-
sions and to access data from the devices. The MX7575
and MX7576 have two common interface modes: slow-
memory interface mode and ROM interface mode. In
addition, the MX7576 has an asynchronous conversion
mode (MODE pin = low) where continuous conversions
are performed. In the slow-memory interface mode, CS
and RDare taken low to start a conversion and they
remain low until the conversion ends, at which time the
conversion result is latched. This mode is designed for
µPs that can be forced into a wait state. In the ROM
interface mode, however, the µP is not forced into a wait
state. A conversion is started by taking CSand RDlow,
and data from the previous conversion is read. At the
end of the most recent conversion, the µP executes a
read instruction and starts another conversion.
For the MX7575, TP should be hard-wired to VDDto
ensure proper operation of the device. Spurious signals
may occur on TP, or excessive currents may be drawn
from VDDif TP is left open or tied to a voltage other than
VDD.
Slow-Memory ModeFigure 3 shows the timing diagram for slow-memory
interface mode. This is used with µPs that have a wait-
state capability of at least 10µs (such as the 8085A),
where a read instruction is extended to accommodate
slow-memory devices. A conversion is started by exe-
cuting a memory read to the device (taking CSand RD
low). The BUSYsignal (which is connected to the µP
READY input) then goes low and forces the µP into a
wait state. The MX7575 track/hold, which had been
tracking the analog input signal, holds the signal on the
third falling clock edge after RDgoes low (Figure 12).
The MX7576, however, samples the analog input eight
times during a conversion (once before each compara-
tor decision). At the end of the conversion, BUSY
returns high, the output latches and buffers are updat-
ed with the new conversion result, and the µP com-
pletes the memory read by acquiring this new data.
The fast conversion time of the MX7575/MX7576
ensures that the µP is not forced into a wait state for an
excessive amount of time. Faster versions of many µPs,
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
_______________________________________________________________________________________5Figure 2. Load Circuits for Data-Hold Time Test
MX7575/MX7576including the 8085A-2, test the status of the READY
input immediately after the start of an instruction cycle.
Therefore, if the MX7575/MX7576 are to be effective in
placing the µP in a wait state, their BUSYoutput should
go low very early in the cycle. When using the 8085A-2,
the earliest possible indication of an upcoming read
operation is provided by the S0 status signal. Thus, S0,
which is low for a read cycle, should be connected to
the RDinput of the MX7575/MX7576. Figure 4 shows
the connection diagram for the 8085A-2 to the
MX7575/MX7576 in slow-memory interface mode.
ROM Interface ModeFigure 5 shows the timing diagram for ROM interface
mode. In this mode, the µP does not need to be placed
in a wait state. A conversion is started with a read
instruction (RDand CSgo low), and old data is
accessed. The BUSYsignal then goes low to indicate
the start of a conversion. As before, the MX7575
track/hold acquires the signal on the third falling clock
edge after RDgoes low, while the MX7576 samples it
eight times during a conversion. At the end of a conver-
sion (BUSYgoing high), another read instruction always
accesses the new data and normally starts a second
conversion. However, if RDand CSgo low within one
external clock period of BUSYgoing high, then the sec-
ond conversion is not started. Furthermore, for correct
operation in this mode, RDand CSshould not go low
before BUSYreturns high.
Figures 6 and 7 show the connection diagrams for
interfacing the MX7575/MX7576 in the ROM interface
mode. Figure 6 shows the connection diagram for the
6502/6809 µPs, and Figure 7 shows the connections for
the Z-80.
Due to their fast interface timing, the MX7575/MX7576
will interface to the TMS32010 running at up to 18MHz.
Figure 8 shows the connection diagram for the
TMS32010. In this example, the MX7575/MX7576 are
mapped as a port address. A conversion is initiated by
using an IN A and a PA instruction, and the conversion
result is placed in the TMS32010 accumulator.
Asynchronous Conversion Mode (MX7576) Tying the MODE pin low places the MX7576 into a con-
tinuous conversion mode. The RDand CSinputs are
only used for reading data from the converter. Figure 9
shows the timing diagram for this mode of operation,
and Figure 10 shows the connection diagram for the
8085A. In this mode, the MX7576 looks like a ROM to
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs_______________________________________________________________________________________Figure 3. Slow-Memory Interface Timing Diagram
Figure 4. MX7575/MX7576 to 8085A-2 Slow-Memory Interface
Figure 5. ROM Interface Timing Diagram
Figure 6. MX7575/MX7576 to 6502/6809 ROM Interface
