MX7534KN+ ,Microprocessor-Compatible, 14-Bit DACsGeneral Description ________
MX7534KP+ ,Microprocessor-Compatible, 14-Bit DACsFeaturesThe MX7534/MX7535 are high-performance, CMOS, ♦ 14-Bit Monotonic Over Full Temperature Rang ..
MX7535JN ,Microprocessor-Compatible / 14-Bit DACsFeaturesThe MX7534/MX7535 are high-performance, CMOS, ' 14-Bit Monotonic Over Full Temperature Rang ..
MX7535KN ,Microprocessor-Compatible / 14-Bit DACsMX7534/MX753519-1116; Rev 1; 11/96Microprocessor-Compatible,14-Bit DACs_______________
MX7535KP+ ,Microprocessor-Compatible, 14-Bit DACsMX7534/MX753519-1116; Rev 1; 11/96Microprocessor-Compatible,14-Bit DACs_______________
MX7535SQ ,Microprocessor-Compatible / 14-Bit DACsApplicationsMX7534AQ -25°C to +85°C 20 CERDIP ±2MX7534BD -25°C to +85°C 20 Ceramic SB ±1Machine and ..
NDS356P ,P-Channel Logic Level Enhancement Mode Field Effect Transistor
NDS7002 ,N-Channel Enhancement Mode Field Effect Transistorapplications.______________________________________________________________________________________ ..
NDS7002 ,N-Channel Enhancement Mode Field Effect TransistorElectrical Characteristics T = 25°C unless otherwise notedASymbol Parameter Conditions Type Min Typ ..
NDS8410A ,Single N-Channel Enhancement Mode Field Effect TransistorMarch 1997 NDS8410ASingle N-Channel Enhancement Mode Field Effect Transistor
NDS8410S ,Single N-Channel Enhancement Mode Field Effect TransistorELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)ASymbol Parameter Conditions Min Typ Ma ..
NDS8425 ,Single N-Channel, 2.5V Specified PowerTrench MOSFETNDS8425January 2001NDS8425 Single N-Channel, 2.5V Specified PowerTrench MOSFET
MX7534JP+-MX7534KN+-MX7534KP+-MX7535KP+
Microprocessor-Compatible, 14-Bit DACs
_______________General DescriptionThe MX7534/MX7535 are high-performance, CMOS,
monolithic, 14-bit digital-to-analog converters (DACs).
Wafer-level, laser-trimmed, thin-film resistors and tempera-
ture-compensated NMOS switches assure operation over
the full operating temperature range with exceptional lin-
ear and gain stability.
The MX7534 accepts right-justified data in two bytes from
an 8-bit bus, while the MX7535 operates with a 14-bit data
bus with separate MS-byte and LS-byte select controls. In
addition, all digital inputs are compatible with both TTL and
5V CMOS-logiclevels. The MX7534/MX7535 are intended
for unipolar operation, but may be operated as bipolar
DACs with additional external components. Both devices
are protected against CMOS latchup, and neither requires
the use of external Schottky protection diodes.
The MX7534 is available in 20-pin narrow (0.3") DIP, wide
SO, or PLCC packages. The MX7535 is available in
28-pin, 600 mil wide DIP, wide SO, or PLCCpackages.
________________________ApplicationsMachine and Motion Control Systems
Automatic Test Equipment
Digital Audio
μP-Controlled Calibration Circuitry
Programmable-Gain Amplifiers
Digitally Controlled Filters
Programmable Power Supplies
____________________________Features14-Bit Monotonic Over Full Temperature RangeFull 4-Quadrant MultiplicationμP-Compatible, Double-Buffered InputsExceptionally Low Gain Tempco (2.5ppm/°C)Low Output Leakage (<20nA)Over Temp.Low Power ConsumptionTTL and CMOSCompatible
______________Ordering Information
Ordering Information continued at end of data sheet.*Dice are tested at +25°C, DC parameters only.
icroprocessor-Compatible,4-Bit DACs
________________________________________________________________Maxim Integrated Products1MX7534
DAC REGISTER
MS
INPUT
REGISTER
LS
INPUT
REGISTER867–14
14-BIT DAC
CONTROL
LOGICREF
RFB
IOUT
AGNDS
AGNOF
VDD
D7–D0DGNDVSS
Functional diagrams continued at end of data sheet.
_______________Functional Diagrams_________________Pin Configurations19-1116; Rev 1; 11/96
& the latest literature: http://,
PARTTEMP. RANGEPIN-PACKAGEINL (LSBs)
MX7534KN0°C to +70°C20 Plastic DIP±1
MX7534JN0°C to +70°C20 Plastic DIP±2
MX7534KCWP0°C to +70°C20 SO±1
MX7534JCWP0°C to +70°C20 SO±2
MX7534KP0°C to +70°C20 PLCC±1
MX7534JP0°C to +70°C20 PLCC±2
MX7534J/D0°C to +70°CDice*±2
MX7534BQ-25°C to +85°C20 CERDIP±1
MX7534AQ-25°C to +85°C20 CERDIP±2
MX7534BD-25°C to +85°C20 Ceramic SB±1
MX7534AD-25°C to +85°C20 Ceramic SB±2
MX7534KEWP-40°C to +85°C20 SO±1
MX7534JEWP-40°C to +85°C20 SO±2
MX7534TQ-55°C to +125°C20 CERDIP±1
MX7534SQ-55°C to +125°C20 CERDIP±2
MX7534TD-55°C to +125°C20 Ceramic SB±1
MX7534SD-55°C to +125°C20 Ceramic SB±2
VSS
VDDAGNDS
IOUT
RFB
REF
TOP VIEWD6
DGND
AGNDFD4
MX7535 at end of data sheet.
DIP/SO/PLCC/Ceramic SBMX7534
Microprocessor-Compatible,4-Bit DACs_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +11.4V to +15.75V (Note 1), VREF= 10V, VIOUT= VAGNDS= VSS= 0V, TA= TMINto TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto DGND............................................................-0.3V, +17V
VSSto AGND.............................................................-15V, +0.3V
REF to AGND (MX7534)......................................................±25V
REFS to AGND (MX7535)....................................................±25V
REFF to AGND (MX7535)....................................................±25V
RFB to AGND.......................................................................±25V
Digital Input Voltage to DGND.........................-0.3V, VDD+ 0.3V
IOUT to DGND.................................................-0.3V, VDD+ 0.3V
AGND to DGND...............................................-0.3V, VDD+ 0.3V
Continuous Power Dissipation (TA= +70°C)
20-Pin Plastic DIP(derate 11.11mW/°C above +70°C)....889mW
28-Pin Plastic DIP (derate 14.29mW/°C above +70°C)......1.14W
20-Pin SO(derate 10.00mW/°C above +70°C)..............800mW
28-Pin SO (derate 12.50mW/°C above +70°C).....................1W
20-Pin PLCC (derate 10.00mW/°C above +70°C).........800mW
28-Pin PLCC (derate 10.53mW/°C above +70°C).........842mW
20-Pin CERDIP (derate 11.11mW/°C above +70°C)......889mW
28-Pin CERDIP (derate 16.67mW/°C above +70°C)........1.33W
20-Pin Ceramic SB
(derate 11.76mW/°C above +70°C).............................941mW
28-Pin Ceramic SB
(derate 20.00mW/°C above +70°C)................................1.6W
Operating Temperature Ranges
MX753_J/K............................................................0°C to +70°C
MX753_A/B........................................................-25°C to +85°C
MX753_EW_.......................................................-40°C to +85°C
MX753_S/T.......................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
±10Input Leakage CurrentμA±1
VINLInput Low VoltageV0.82.4VINHInput High Voltage3.5610RREFReference Voltage Input
Resistance (Note 3)
±150
IOUTOutput Leakage Current
Bits14Resolution
±25
ppm/°C±0.5±5
Gain Temperature Coefficient
(Note 2)
±0.5±2.5
LSB±2INLRelative Accuracy
LSB
Full-Scale Error
UNITSMINTYPMAXSYMBOLPARAMETERMX753_K/B/T= TMINto TMAX
MX753_J/K/A/B
MX753_J/A/S
Measured with internal RFB,
includes effects of leakage
current and gain TC
MX753_S/T
CONDITIONSLSB±1Guaranteed MonotonicDifferential Nonlinearity7CINInput Capacitance (Note 2)= TMIN
to TMAX
All digital
inputs at 0V
All digital
inputs at 0V,
VSS= 0V= +25°C
MX753_J/A/S
MX753_K/B/T
MX753_J/A/S
MX753_K/B/T= +25°CDigital inputs
at 0V or VDD
DC ACCURACY
REFERENCE INPUT
DIGITAL INPUTS
icroprocessor-Compatible,4-Bit DACs_______________________________________________________________________________________3-200-500VSSNegative Supply-Voltage Range11.415.75VDDPositive Supply-Voltage Range3IDDPositive Supply Current500ISSNegative Supply Current
UNITSMINTYPMAXSYMBOLPARAMETERFor specific performance
For specific performance
MX7534
MX7535
Digital inputs at 0V or VDD
CONDITIONSDigital inputs at
VINHor VINL
ELECTRICAL CHARACTERISTICS (continued)(VDD= +11.4V to +15.75V (Note 1), VREF= 10V, VIOUT= VAGNDS= VSS= 0V, TA= TMINto TMAX, unless otherwise noted.)
mVp-p
nV-sec500.81.5Output Current Setting Time
Digital-to-Analog Glitch Impulse
nV/Hz15Output Noise Voltage Density
(10Hz–100kHz)
130COUTOutput Capacitance (IOUT Pin)
Multiplying Feedthrough Error
(Note 5)
%/%±0.01
±0.02Power-Supply Rejection260
UNITSMINTYPMAXSYMBOLPARAMETER= +25°C
Measured with VREF= 0V,
IOUT loads = 100ΩII 13pF, DAC register
alternately loaded with all 1s and all 0s= +25°C, to 0.003% of full-scale range,
IOUT load = 100ΩII 13pF, DAC register
alternately loaded with all 1s and all 0s
Measured between RFBand IOUT
DAC register loaded with all 0s= TMIN to TMAX= +25°C= TMIN to TMAX
DAC register loaded with all 1s
CONDITIONSVREF= ±10V, 10kHz
sine wave, DAC register
loaded with all 0s
ΔVDD= ±5%
Note 1:Specifications are guaranteed for VDDof +11.4V to +15.75V. At VDD= +5V, device is still functional with degraded specifications.
Note 2:Guaranteed by design, not tested.
Note 3:Resistors have a typical -300ppm/°C tempco.
AC PERFORMANCE CHARACTERISTICS (Note 4)(VDD= +11.4V to +15.75V, VREF= 10V, VIOUT= VAGND(VAGNDSfor MX7535) = VSS= 0V, output amplifier is AD544*,= TMINto TMAX, unless otherwise noted.)
Note 4:These characteristics are included for design guidance only, and are not subject to test.
Note 5:Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND.
* AD544 is an Analog Devices part.
POWER REQUIREMENTS
Microprocessor-Compatible,4-Bit DACs_______________________________________________________________________________________
TIMING CHARACTERISTICS (MX7534)(VDD= +11.4V to +15.75V, VREF= 10V, VIOUT= VAGND= VSS= 0V, TA= TMINto TMAX, unless otherwise noted. See Figure 1a for
timing diagram.)
1700t20t1CSMSBor CSLSBto WRSetup Time
CSMSBor CSLSBto WRHold Time
240Write Pulse Width
240LDACPulse Width
UNITSMINTYPMAXSYMBOLPARAMETER= +25°C= -55°C to +125°C= -25°C to +85°C= -55°C to +125°C= +25°C= -25°C to +85°C
CONDITIONS140Data-Hold Time
180Data-Setup Time= +25°C= -55°C to +125°C= -25°C to +85°C= -55°C to +125°C= +25°C= -25°C to +85°C
TIMING CHARACTERISTICS (MX7535)(VDD= +11.4V to +15.75V, VREF= 10V, VIOUT= VAGNDS= VSS= 0V, TA= TMINto TMAX, unless otherwise noted. See Figure 1b for
timing diagram.)0t20t1Address Valid to Write Setup Time
Address Valid to Write Hold TimeData Hold TimeData Setup Time
UNITSMINTYPMAXSYMBOLPARAMETER= +25°C= -55°C to +125°C= -25°C to +85°C= -55°C to +125°C= +25°C= -25°C to +85°C
CONDITIONS240Write Pulse Width
200= -55°C to +125°C= +25°C= -25°C to +85°C
Chip-Select to Write-Hold Time
Chip-Select to Write-Setup Time
icroprocessor-Compatible,4-Bit DACs_______________________________________________________________________________________5
__________Pin Description (MX7534)
NAMEFUNCTIONREFReference Input to DACRFB
PINIOUTCurrent OutputAGNDS
Analog Ground Sense. Reference
point for external circuitry. AGNDS
should carry minimum current.D6Data Bit 6D7Data Bit 7DGNDDigital GroundAGNDF
Analog Ground Force. Carries current
from internal analog ground connec-
tions. AGNDS and AGNDF are tied
together internally.
Feedback Resistor. Used to close the
loop around an external op amp.
__________Pin Description (MX7535)
NAMEFUNCTIONREFSReference Voltage SenseREFF
PINRFBFeedback Resistor. Used to close the
loop around an external op amp.AGNDS
Analog Ground Sense. Reference
point for external circuitry. This pin
should carry minimum current.D12Data Bit 12D13Data Bit 13 (MSB)DGNDDigital GroundAGNDF
Analog Ground Force. Carries current
from internal analog ground
connections. AGNDS and AGNDF
are tied together internally.
IOUTCurrent OutputD10Data Bit 10D11Data Bit 11D8Data Bit 8D9Data Bit 9
Reference Voltage ForceD3Data Bit 3 or Data Bit 11D4Data Bit 4 or Data Bit 12D5Data Bit 5 or Data Bit 13 (MSB)D0Data Bit 0 (LSB) or Data Bit 8D1Data Bit 1 or Data Bit 9D2Data Bit 2 or Data Bit 10WRWrite Input. Active low.A0Address Input 0A1Address Input 1VSSBias pin for high-temperature,
low-leakage configurationVDD+12V to +15V Supply-Voltage InputCSChip-Select Input. Active low.D7Data Bit 7D6Data Bit 6D5Data Bit 5D1Data Bit 1D4Data Bit 4D3Data Bit 3D2Data Bit 2D0Data Bit 0 (LSB)CSMSBChip-Select Most Significant Byte.
Active low.LDACAsynchronous Load DAC Input.
Active low.CSLSBChip-Select Least Significant Byte.
Active low.WRWrite Input. Active low.N.C.No Connection. Not internally connected.VDD+12V to +15V Supply-Voltage InputVSSBias pin for high-temperature,
low-leakage configuration
_______________Detailed Description
Digital-to-Analog SectionThe basic MX7534/MX7535 digital-to-analog converter
(DAC) circuit consists of a laser-trimmed, thin-film,
11-bit R-2R resistor array, a 3-bit segmented resistor
array, and NMOS current switches, as shown in Figure
2. The three MSBs are decoded to drive switches A–G
of the segmented array, and the remaining bits drive
switches S0–S10 of the R-2R array.
Binary weighted currents are switched to either AGNDF
or IOUT, depending on the status of each input bit. The
R-2R ladder current is one-eighth of the total reference
input current. The remaining seven-eighths of the cur-
rent flows in the segmented resistors, dividing equally
among these seven resistors. The input resistance at
REF is constant; therefore, it can be driven by a voltage
or current source of positive or negative polarity.
The MX7534/MX7535 are optimized for unipolar output
operation (analog output from 0V to -VREF), although
bipolar operation (analog output from +VREFto -VREF) is
possible with some added external components.
Figure 3 shows the equivalent circuit for the two DACs.
COUTvaries from about 90pF to 180pF, depending on
the digital code. R0denotes the DAC’S equivalent out-
put resistance, which varies with the input code.
g(VREF,N) is the Thevenin equivalent voltage generator
due to the reference input voltage, VREF, and the trans-
fer function of the R-2R ladder, N.
Digital SectionAll digital inputs are both TTL and 5V CMOS logic compat-
ible. The digital inputs are protected from electrostatic dis-
charge (ESD) with typical input currents of less than 1nA.
To minimize power-supply currents, keep digital input volt-
ages as close to 0V and 5V logic levels as possible.
__________Applications Information
Unipolar Operation (2-Quadrant
Multiplication)Figures 4a and 4b show the circuit diagram for unipolar
binary operation. With an AC input, the circuit performs
2-quadrant multiplication. The code table for Figure 4 is
given in Table 2.
Capacitor C1 provides phase compensation and helps
prevent overshoot and ringing when high-speed op
amps are used. Note that the output polarity is the
inverse of the reference input.
Microprocessor-Compatible,4-Bit DACs_______________________________________________________________________________________VIH + VIL
NOTES:
1) ALL INPUT-SIGNAL RISE AND FALL TIMES ARE MEASURED FROM 10% TO 90%
OF +5V. tR = tF = 20ns.
2) TIMING MEASUREMENT REFERENCE LEVEL ISt6t2t4
A0,A1
DATAWRt5t6t5t1t2
NOTES:
1) ALL INPUT-SIGNAL RISE AND FALL TIMES ARE MEASURED FROM 10% TO 90%
OF +5V. tR = tF = 20ns.2) TIMING MEASUREMENT REFERENCE LEVEL IS
3) IF LDAC IS ACTIVATED PRIOR TO THE RISING EDGE OF WR, THEN IT MUST
STAY LOW FOR t3 OR LONGER AFTER WR GOES HIGH.
VIH + VIL
CSLSB
CSMSB
LDAC
DATA
Figure 1a. MX7534 Timing DiagramFigure 1b. MX7535 Timing Diagram
icroprocessor-Compatible,4-Bit DACs_______________________________________________________________________________________7
Zero-Offset Adjustment
(Figures 4a and 4b)Load the DAC register with all 0s.Adjust the offset of amplifier A1 so that V0(see fig-
ure) is at a minimum (i.e., ≤30μV).
Gain Adjustment
(Figures 4a and 4b)Load the DAC register with all 1s.Trim potentiometer R1 so that VOUT= -VIN(16383)16384
In fixed-reference applications, adjust full scale by
omitting R1 and R2 and trimming the reference voltage
magnitude. In many applications, the excellent Gain
Tempco and Gain Error specifications eliminate the
need for gain adjustment. However, if trims are
required and the DAC is to operate over a wide temper-
ature range, use low-tempco (>300ppm/°C) resistors.
Bipolar Operation
(4-Quadrant Multiplication)Bipolar or 4-quadrant operation is shown in Figures 5a
and 5b. This configuration provides for offset binary
coding. Table 4 shows DAC codes and the corre-
sponding analog outputs for Figures 5a and 5b. With
the DAC loaded to 10 0000 0000 0000, either adjust R1
for VOUT= 0V, or omit R1 and R2 and adjust the ratio of
R5 and R6 for VOUT= 0V. Adjust the amplitude of VIN
or vary the value of R7 for full-scale trimming.
Resistors R5, R6, and R7 must be matched to 0.003%.
Mismatch of R5 and R6 causes both offset and full-
scale errors. For wide temperature range operation,
use resistors of the same material so that their tempera-
ture coefficients match and track.2RFEDCBAS10S9S02R2R2R2R2R2RRR2R
R/4
RFB
IOUT
AGNDS
AGNDF
*NOTE: VALID FOR MX7535. IN MX7534, 0REFS AND 0REFF ARE REPLACED BY ONE PIN: REF.REFS*
REFF*
R/4
AGNDS
AGNDF
IOUT
RFB
ILEAKAGEg(VREF, N)COUT
Figure 2. Simplified Circuit Diagram
Figure 3. Equivalent Analog Output Circuit
Table 1.MX7534 Logic StatesCS
A1A2FUNCTION1XXDevice not selected (Note 1)XXXNo data transfer000DAC loaded directly from
Data Bus (Note 2)001MS Input Register loaded
from Data Bus010LS Input Register loaded
from Data Bus011DAC Register loaded from
Input Registers
Note 1:X = Don’t Care.
Note 2:When A1 = 0 and A0 = 0, all DAC registers are trans-
parent. By placing all 0s or all 1s on the data inputs, the
user can load the DAC to zero or full-scale output in
one write operation. This simplifies system calibration.
Grounding ConsiderationsSince IOUT and the output amplifier noninverting input
are sensitive to offset voltages, connect nodes that
must be grounded directly to a single-point ground
through a separate, very-low-resistance path. Note that
the output currents at IOUT and AGNDF vary with input
code and create code-dependent error if these termi-
nals are connected to ground (or a virtual ground)
through a resistive path.
To obtain high accuracy, it is important to use a proper
grounding technique. The two AGND pins (AGNDF‚
AGNDS) provide flexibility in this respect. In Figures 4a
and 4b, AGNDS and AGNDF are shorted together
externally and an extra op amp, A2, is not used.
Voltage-drops due to bond-wire resistance are not
compensated for in this circuit; this could create a lin-
earity error of approximately 0.1LSB due to bond-wire
resistance alone. This can be eliminated by using the
circuits shown in Figures 6a and 6b, where A2 main-
tains AGNDS at signal ground potential. By using
force/sense techniques, all switch contacts on the DAC
are kept at exactly the same potential, and any error
caused by bond-wire resistance is eliminated.
Figure 7 shows a remote voltage reference driving the
MX7535. Op amps A2 and A3 compensate for voltage
drops along the reference input line and analog
ground line.
Figure 8 shows a printed circuit board (PCB) layout withsingle output amplifier for the MX7534. The input to
REF (Pin 1) is shielded to reduce AC feedthrough, while
the digital inputs are shielded to minimize digital
feedthrough. The traces connecting IOUT and AGNDS
to the inverting and noninverting op amp inputs are
kept as short as possible. Gain trim components, R3
and R4, are omitted.
Zero-Offset Adjustment
(Figures 6a and 6b)Load DAC register with all 0s.Adjust offset of amplifier A2 for minimum potential at
AGNDS. This potential should be ≤30μV with respect
to signal ground.Adjust A1’s offset so that VOUTis at a minimum
(i.e., ≤30μV).
Microprocessor-Compatible,4-Bit DACs_______________________________________________________________________________________
Table 2.Unipolar Binary Code Table
BINARY NUMBER IN
DAC REGISTER
ANALOG OUTPUT
(VOUT)MSBLSB111111111111000000000000000000000001000000000000
-VIN(16383)16384
-VIN( 8192) = - 1VIN163842
-VIN(1 )16384
R1
100W
R2
33W
INPUT
DATA
ANALOG
GROUND
7–1420191C1
33pF
VDD
VIN
VSS
MX7534
REFRFB
IOUT
AGNDS
AGNDFDGNDD7–D0-VO
R1
20W
R2
10W
INPUT
DATA
ANALOG
GROUND
LDAC
CSMSB
CSLSB272261C1
33pFVDD
VIN
VSS
MX7535
REFFREFSRFB
IOUT
AGNDS
AGNDFDGNDD13–DOVO
Figure 4a. Unipolar Binary OperationFigure 4b. Unipolar Binary Operation
