MX7524JCSE- ,CMOS 8-Bit Buffered Multiplying DACsFeatures
. Microprocessor Compatible
. On-Chip Data Latches
. Guaranteed Monotonie Over Temp.
. ..
MX7524JESE ,Improved MX7524Wuan-eDem.
194173, Rev f 7/95
lVI/J X I/VI
CMOS B-Bit Buffered Multiplying DACs
MX7524JN ,CMOS 8-Bit Buffered Multiplying DACsELECTRICAL CHARACTERISTICS-MXN" +5V Operation
(Va, = +5V; VREF = +10V; VOUT1 = VOUT2 = 0V; TA = ..
MX7524KCSE ,CMOS 8-Bit Buffered Multiplying DACsGeneral Description
The MX7524 and MAX7624 are CMOS 8-bit digital-to-
analog converters (DAC) w ..
MX7524KESE ,Improved MX7524Applications
pp Controlled Gain
Function Generators
Bus Structured Instruments
Automatic Te ..
MX7524KN ,CMOS 8-Bit Buffered Multiplying DACsApplications
pp Controlled Gain
Function Generators
Bus Structured Instruments
Automatic Te ..
NDS351AN_NL ,N-Channel, Logic Level, PowerTrench MOSFETapplications in notebook computers, portable phones,• Industry standard outline SOT-23 surface moun ..
NDS352AP ,P-Channel Logic Level Enhancement Mode Field Effect TransistorGeneral Description
NDS352AP_NL ,P-Channel Logic Level Enhancement Mode Field Effect TransistorElectrical Characteristics (T = 25°C unless otherwise noted)ASymbol Parameter Conditions Min Typ Ma ..
NDS352AP_NL ,P-Channel Logic Level Enhancement Mode Field Effect Transistorapplicationsusing proprietary SuperSOT -3 design for superior thermalsuch as notebook computer pow ..
NDS352P ,P-Channel Logic Level Enhancement Mode Field Effect TransistorMarch 1996NDS352P P-Channel Logic Level Enhancement Mode Field Effect Transistor
NDS355 ,N-Channel Logic Level Enhancement Mode Field Effect TransistorElectrical Characteristics (T = 25°C unless otherwise noted)ASymbol Parameter Conditions Min Typ Ma ..
MX7524JCSE--MX7524JN-MX7524KCSE-MX7524LN
CMOS 8-Bit Buffered Multiplying DACs
19-0773, Flev l: 7/95
2fllALt'llDi)ClLfiM]
CMOS 8-Bit Buffered Multiplying DACs
General Description
The MX7524 and MAX7624 are CMOS 8-bit digital-to-
analog converters (DAC) which will interface directly
with most microprocessors. On-chip input latches
make the DAQ-interface similar to a RAM write cycle
where CS and WR are the only control inputs required.
Linearity up to th LSB is available (MX7524LAVU
grades) and power consumption is less than lOmW.
Monotonicity is guaranteed over the full temperature
range.
For the MX7524, +5V TTL and CMOS logic compati-
bility is guaranteed when using +5V power. Over the
supply range of +5V to +15V, all logic inputs are high
voltage CMOS compatible.
The MAX7624 has +5V TTL/CMOS compatible inputs
for a +12V to +15V supply range.
Applications
pp Controlled Gain
Function Generators
Bus Structured Instruments
Automatic Test Equipment
Digital Control Systems
_0_ Typical Operating Circuit
Features
. Microprocessor Compatible
. On-Chlp Data Latches
. Guaranteed Monolonlc Over Temp.
. Low Power Consumption
. 8, 9, and 10-Blt Linearity
. MXTS24 TTL/CMOS Compatible at 'sy
o MAX7624 TTL/CMOS Compatible at +12V to +15V
Ordering Information
PART TEMP. RANGE PACKAGE' ERROR
MX7524JN tPC to +70°c Plastic DIP th LSB
MX7524KN tPC to +70°c Plastic DIP 1% LSB
MX7524LN tPC to +70°c Plastic DIP kh LSB
MX7524JCSE tPC to +70°C Small Outline iv: LSB
MX7524KCSE 0°C to +70°c Small Outline 12% LSB
MX7524LCSE 0''C to +70°C Small Outline 1% LSB-
Mx7524J/b 0°C to '70''C Dice iv: LSB
MX7524AD -25°C to r85''C Ceramic iv: LSB
MX7524BD -25''C to +85°C Ceramic fr/a LSB
MX75240D -25°C to +85°C Ceramic Ah LSB
. All devices - 16 lead packages
.. Manm reserves the right to ship Ceramic packages in lieu of
CERDIP packages
(Ordering information continued on last page)
Pin Configuration
VllEF Van
mm pg 4
ums tr,
W8o-il3
H Vnur
tltt0 m nun n2 ussu (mu IF cam
musmm IS neoumm
Unipolar Binary Operation
(2-Quadrant Multiplication)
' wzngVW/rbzszxw
Top View
OUT] 1 V E Rrsmucx
OUT CE E llm
tlilo E MAXIM 31E)
087 M881 E MX7524 El Wit
Mii E MAX7624 ER
ilim E Es] 080 Mill
ilM [E E ilN
M3 [E E M
Maxim Integrated Products 1
0a" ton free 1-800-998-8800 for free samples or literature.
MX 7524/ MAX 7624
CMOS 8-Bit Buffered Multiplying DACs
ABSOLUTE MAXIMUM RATINGS- MX7524, MAX7624
Von to GND ...... -0.3V. +17V Operating Temperature Ranges (continued)
VREF to GND ............. t25V MX7524AD. AO, BD, BO, CD, co ..w. -25''C to +85°C
Vnra to GND ...................................... A25V MAX7624EPE ........................ -40'C to HMPC
Digital Input Voltage to GND ........ -0.3V to V00 ' 0.3V MX7524SD, so, TD, TO. UD, U0
OUT1, OUT2 to GND ........................ -0.3V, V00 MAX7624MJE ...................... -55°C to '125''C
Operating Temperature Ranges Storage Temperature Range ........... -65°C to +160°C
MX7524JN, KN, LN, JCSE, KCSE, LCSE Power Dissipation (any Package) to +75°C ...... 450mW
MAX7624CPE, CSE ..................... tPC to +70°C Derate Above +75°C by ..................... 6 mW/°C
Lead Temperature (Soldering 10 seconds) ....... +300''C
Stream above those listed under “Absolute Maximum Ratings" may cause permanen! damage to the devices. These are stress ratings only, and
(uncgmnal operation of the device at these or any other conditions above those itttiitttttttd in the operational sections of the sptmititatt'ons is not
Implied. Exposure to absolute maximum ratings conditions for extended period: may allect device reliability.
ELECTRICAL CHARACTERISTICS-MF, +5V Operation
(VDD = +5V; VREF = +10V; Vour, = Vou12 = 0V; T, = Tum to TMAX unless otherwise noted)
PARAMETER lsvwsoLl commons I MIN TYP MAX [UNITS
DC ACCURACY
Resolution 8 Bits
J,A,S 11/2
Relative Accuracy INL K,B,T tl/it LSB
L,C,U 11/2
. ' . . All Grades Guaranteed
Differential Non-Linearity DNL Monotonic Over Temp. ll LSB
. T = 25''C Aiyh
E 1 A LSB
Gain rror (Note ) TA = Tum to me 13'4
Gain Temp. Coefficient a
(Note 2, 3) " 140 ppm/ C
' ' - T, = 25°C 0.002 0.08 tt 0
Supply Rejection (Note 2) PSR AVDD - 110% TA = Tum to TMAX 0.01 0.16 loFSR/ /o
Output Leakage Current Vnsr = A10V T, = 25°C 150 nA
(loun) DAC is 00000000 T, = TMIN to me i400
Output Leakage Current VREF = S101/ TA = 25°C $50 nA
(low) me is 11111111 T, = Tum to TMAX 1400
REFERENCE INPUT
Rm (pin 15 to GND) l l 5 10 20 m
DYNAMIC PERFORMANCE
£00131 = ov to Voo to OV
Output Current Settling-Time WR = CS = 0V TA = 25°C 400 ns
to 1/2 LSB (Note 2) OUT1 Load = 1000. T, = TM.N to TMAX 500
05x1 = 13pF;
vREF = i10V
AC Feedthrough 100kHz Sintyyzve TA = 25''C 0.25 %FSR
(OUT1 or OUT2) (Note 2) D_BP-DB7 = WR = TA = TM,N to TMAX 05
CS = 0V
ANALOG OUTPUTS
. Cour DB0-DB7 = Vnoi W --dlTs = ov 120
OUT1 Capacitance (Note 2) l DBO-DB7 = 0V; 'vii = CS = ov 30 pF
_ co " 0130037 = vos-im =_c_s = ov 30
OUT2 Capacitance (Note 2) U D80-DB7 = 0V; WR = CS = 0V 120 pF
Note 1: Gain error is measured using internal feedback resistor, Full Scale Range (FSR) = VREF.
Note 2: Guaranteed. but not tested.
Note 3: Gain error measured from 25''C to TMAX or from 25°C to TMIN.
Note 4: Sample tested at 25''C to ensure compliance.
ll/l/J X I IV!
