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MTC50150-TB-C2
ADSL GATEWAY PROCESSOR
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MTC50150September 2004
GENERAL FEATURES
1.1 WAN modem feature set Embedded transceiver ANSI T1.413, ITU G.dmt
Annex A/B incl. Deutsche Telecom UR-2
compliant, splitterless ITU G.Lite ADSL analog front end compatibility: MTC20174, ADSL front end, 7th generation,
integrated line driver, DCXO
1.2 WAN connectivity Point to point protocol over Ethernet Point to point protocol over ATM Relay via PPP session control on terminal CIP classical IP over Ethernet Full ICSA firewall
1.3 Session Control PPPoE point to point protocol over Ethernet PPPoA point to point protocol over ATM PPPoA relay via PPP session control on
terminal.
1.4 ATM features Adaptation Layers: AAL5 (data), supported in
hardware Encapsulation: RFC1483 and RFC2684, multi
protocol encapsulation over ATM (MPOA) over
AAL5 bridged and routed modes ATM circuit: 8 PVC Available services (Qos): UBR
1.5 LAN feature set 1 Ethernet 10/100 MII (HPNA compatible) 2 UARTs, Bluetooth compatible Bridging: Transparent bridge: IEEE 801.1d,
spanning tree, learning/filter bridge in hardware Embedded router: RIP1, RIP2, static routing NAT/PAT with extended ALG support DHCP server/client IP protocol: TCP/IP, ARP sharing access,
ICMP, IGMP Support up to 128 MAC stations. Embedded http server for configuration
1.6 Configuration and Provisioning Configuration: remote configuration via Java™
enabled browser Firmware update: remote upload via network. Management: SNMP, UNI3.1, ILMI 4.0
(management and auto configuration)
1.7 Customization Customization with comprehensive API set Development tool based on Windows
environment on PC Exposed BSP layer Flexible development licenses based on kernel
software in object or source format.
APPLICATION Low cost ADSL residential gateway Residential gateway with broadband ADSL
WAN transceiver Wan to LAN bridge and router with ADSL WAN
transceiver and Ethernet MAC Wireless LAN access point with ADSL WAN
transceiver and Ethernet MAC
DATA BRIEFADSL GATEWAY PROCESSOR
Rev. 1
MTC50150
Figure 2. Block diagram DESCRIPTIONThe MTC50150 is a low cost ADSL bridge and LAN router. One 10/100Mbits Ethernet port allows the con-
nection of a LAN to the WAN in bridged or routed mode. The data traffic can be routed through a local
terminal by using the LAN port. The presence of NAT and DHCP and the API slots for firewall functions
allow for a high-speed connection of LAN connected devices, like PC, to the public Internet in an isolated
and secure environment.
The chip is built around an ARM946ES RISC processor. It embeds a complete ADSL transceiver and LAN
interfaces with an MII allowing multiple medium utilization. A comprehensive software package is available
with the SOC solution, which has been developed with customization in mind. Several software license
plans are available as well as a user friendly development environment.
HARDWARE DESCRIPTIONThe MTC50150 processor combines a DynaMiTe™ ADSL transceiver with a dedicated ARM946ES RISC
processor. To maintain high data throughput, the RISC processor includes 16Kbyte cache memory for
programming and 16Kbyte memory for data. Processing of most of the layer 2 protocols on the ATM (SAR
and AAL) and IP (Mac filter and bridge) sides are performed by specific hardware blocks, relieving the pro-
cessors from these tasks. The chip provides minimal external components and maximum flexibility. In ad-
dition, it contains one Ethernet 10/100 Base-T MAC and the exposed MII interface allows the connection
to alternate LAN mediums like HPNA, WLAN, and HPLUG. The MTC-50150 device is targeted for low-
cost residential gateways. Its primary design goal is to minimize cost. Secondary design goals are: Low system cost using a reduced BOM and optimized SOC technology Low power to facilitate primary service capabilities and thermal system issues Low EMI to simplify packaging and qualification of systems
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MTC50150 HARDWARE FEATURES ARM946ES RISC processor dedicated to network processing, API and DSL modem control Hardware ATM processor: SAR function with AAL5 processing Hardware packet processor: Ethernet MAC, learning and filter bridge One 10/100 Base-T Ethernet MACs with MII interface for external PHY or multi-port switch One 8 or 16-bit wide Flash port, ISA compatible for up to 16Mbyte addressable memory One 32-bit wide SDRAM interface with 32Mbyte addressable memory Interface to MTC20174 DynaMiTe™ ADSL analog front end (AFE) chip Multi-channel DMA engine integrated with peripherals Low power: 1.8V +/-10% core voltage, 3.3V +/- 10% I/O voltage 128 instructions (32 bits) of boot ROM GPIO with support LED Cc-based Multi ICE/compiler support with assembler and debugger Software chip and system simulators for software development and debug JTAG board-level test interface 140MHz system clock (processor cycle clock) Sleep mode with wake on LAN wake on WAN feature Programmable system frequency clock: 140, 105, 70, 35 and 129MHz (fall back mode).
SOFTWARE ARCHITECTUREThe software is organized in 5 clusters: User interface API System services Network services TCP/IP socket ATM encapsulation
A description of the cluster contents is given in the software features section.
MTC50150
Figure 3. Embedded software block diagram SOFTWARE FEATURES
7.1 User Interface APIA development kit dedicated to the platform allows access through the API to specific code sections to
allow software customization. The development kit provides source code for a packet phone application,
drivers and diagnostic software. Other stacks are delivered in the object code. A specific development en-
vironment is provided. It includes project profiling, managing, C compiler/assembler and tools as well a
source level debugger.
7.2 System ServicesMAPI offers an easy interface to control the operations necessary to setup the ADSL link and monitor the
operation conditions. The software provides an optimized control sequence to insure optimum operation
of the DynaMiTe™ chip set.
MIB2: RFC 1213: Management Information Bases (MIB2) is implemented in the device.
RTOS: Implemented RTOS is Posix compliant. The user can access various parts of the software blocks
through specific APIs. Alternate RTOS are planned.
Flash Initialization. Software is stored on an external Flash. At boot-up, the stored software is downloaded
to the device. By using compilation options, software can be executed from the internal RAM (intensive
operations) or executed from the flash. Execution is optimized by the use of an intermediate cache mem-
ory.
Startup initialization: Optional software images can be selected at startup of the device.
Broad Support Program: A BSP layer is provided to allow easy porting of proprietary software on the SOC
architecture. The BSP provides a unique hardware abstraction layer model valid for the entire product line.
This approach allows reuse of the custom solfware through the entire MTC-50xxx product line(*).
(*) starting with MTC-50150
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MTC50150
7.3 Network Services
7.3.1 ILMIEmbedded software provides an ILMI 4.0 implementation which handles address registration (switch to
end device) and notification (end device to switch) as well as auto-configuration. ILMI uses SNMP over
AAL-5 for transport.
7.3.2 UNI Signaling Stackware includes support for standard ATM UNI signaling standards, including UNI 3.1.
7.3.3 RIP1/RIP2 IP Router IP router software provides implementations of RIP1 and RIP2. The IP router is an IPv4 router. Support
for new station discovery is provided.
7.4 TCP/IP Socket
7.4.1 TCPTransport Control Protocol (TCP) is accessed using a standard socket interface to allow easy integration
of existing Layer 3 and higher software into the basic protocol stack.
7.4.2IPInternal protocol: IP and IP routing are both part of the network layer (layer 3). IP is actually responsible
for delivering packets for which the router defines the direction.
7.4.3 DHCP RFC 2131, 2132 Dynamic Host Control Protocol (DHCP) provides both client & server functions. The client is typically used
to obtain an IP address from an ISP. The DHCP server is used to assign local IP client devices with des-
ignated IP addresses. The server lends addresses for a limited time. NAT registers local terminal IP ad-
dresses and maintains a translation table to allow sending and receiving data on the public network by
sharing only the residential gateway assigned public IP address.
7.4.4 NAT: RFC1631, 2663The Network Address Translator (NAT) implements Network and Port Address Translation (NAT/PAT).
NAT allows a single public IP address on the WAN side to be shared among many devices on the LAN
side. Combined with a DHCP server local devices are assigned a private address, hidden to the public
internet and changed frequently. The combination of DHCP and NAT provides a powerful isolation barrier
to external assault. NAT PAT features a number of AGL.
7.5 ATM Encapsulation and spanning-treeRFC 1483/2684 provides a simple robust method of connecting end stations over an ATM network. User
data in the form of Ethernet packets are encapsulated into AAL-5 PDUs for transport over ATM. RFC
1483/2684 provides no AAA function (authentication, authorization & accounting).
7.5.1 Spanning-tree bridge (802.1d)Bridge module provides a transparent bridge between two physically disjoint networks with spanning-tree
option. The spanning-tree algorithm handles redundancy and also increases robustness. It provides high
performance as well as flexibility to group interfaces for example to bridge the WAN only to LAN interfaces
but not to other WAN interfaces.
The ATM driver passes data between application software tasks on the processor and a physical AAL5
hardware block.
MTC50150
7.6 Session Control
7.6.1 PPPoA (RFC 2364) PPP over ATM provides on the CPE side a termination agent for the transportation for IP packets over an
ATM segment. A PPP session is established between the CPE and the central office (DSLAM). PPP pro-
vides AAA function (authentication, authorization and accounting). The PPP packets encapsulated ac-
cording to RFC 2364 for transmission over an ATM segment. On the CPE side, the IP data can be
delivered to the end user over such technologies as Ethernet.
7.6.2 PPPoE (RFC 2516)The PPP over Ethernet encapsulation is used to transport Ethernet PPP traffic. The traffic is then trans-
ported over the ATM link by encapsulating traffic using RFC1483/2683. There may be multiple PPP ses-
sions, each terminated in the IAD client device. PPPoE relay agent works as a enhanced layer 2 bridge.
It determines that which locally originated PPPoE traffic belongs. The relay agent forwards that traffic,
without any unnecessary processing, only to the correct destination. Similarly, received data is immedi-
ately relayed only to the appropriate LAN client.
DEVELOPMENT ENVIRONMENTThe MTC50150 presents a comprehensive set of software features. To allow manufacturers to further cus-
tomize the system, a set of API functions are made available. This use of the API functions requires the
acquisition of a development environment. The development environment is based on the following ele-
ments: -ARM Developer Suite (ADS) v1.1 -ATI Development license -ATI EDE (Embedded Development Environment) -MS Developer Studio (VC++) v6.0 or higher
Along with the development environment a number of tools are provided to allow the diagnostic and the
downloading operation of the executable on the nonvolatile memory of the MTC50150.
NOMINAL CHARACTERISTICSThe MTC50150 processor is available in a 208-pin PBGA (plastic ball grid array) package. All I/Os are
3.3V CMOS levels, with all inputs and 3-states having 5V tolerance. Supply voltages are 1.8 and 3.3V. No
pins have internal pull-ups and pull-downs.
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MTC50150 APPLICATION EXAMPLEThe example below shows the reference design developed for the evaluation board. It is a complete
ADSL-based data gateway that connects to the ADSL enabled phone jack and provides a connection to
a 10/100bT Ethernet port. It utilizes a set of two ASSP available from ST.
The MTC50150 kit is composed of the following elements: A DynaMiTe™ ADSL modem and AFE
(MTC20174). Additional components are SDRAM and Flash memory and Ethernet PHY. Discrete compo-
nents and connectors are not shown on the block diagram. Larger SDRAM and Flash can be connected
to the MTC50150 to store and execute additional (custom) application.
Figure 4. Application block diagramIntensive qualification efforts have been spent on this reference design insuring users of the platform max-
imum interoperability and smooth, rapid design-in, hence reducing engineering effort and Total Time to
Market (TTM).
MTC50150 MTC50150 PIN LIST
11.1 PIN DESCRIPTIONThe pin list comprises of all functional and power supply pins.
A TBGA-208 package (TB208A) is used.
(I = Input, ID = Input with internal Pull-Down, IU= Input with internal Pull-Up, O = Output, B = Bidirectional,
OD = Open Drain, I/OD = Bidirectional with Open Drain output, OZ = High-Z Output, P = Power Supply,
FS = Full Scan, NA = not available as pin).
Table 2. MTC50150 Pin list
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MTC50150
Table 2. MTC50150 Pin list (continued)
MTC50150
Table 2. MTC50150 Pin list (continued)
