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MTC20454
Quad Integrated ADSL CMOS Analog Front End Circuit
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MTC20454February 2004 Fully integrated quad AFE for ADSL Overall 12 bit resolution 1.1MHz signal bandwidth 8.8 MS/s ADC 8.8 MS/s DAC THD: -60 dB @ full scale 1 V full scale input Differential analog I/O Accurate continuous-time channel filtering 3rd & 4th order tuneable continuous time LP
Filters 100 pin TQFP package, Industrial Range
qualified 175 mW power consumption per line
APPLICATIONS ADSL Front-end for high density, low power
central office and digital loop carrier equipment
DESCRIPTIONThe MTC20454 is the first DynaMiTe ADSL (Asyn-
chronous Digital Subscriber Line) analog front end
designed specifically for the central office. It is a
fifth generation Analog Front End (AFE) designed
for DMT based ADSL modems compliant with ITU
G.992.1 and G.992.1 standards. It includes four 12
bit DACs and one 13 bit ADC.
It is intended to be used with the MTC20455 DMT/
ATM processor as part of the MTK20450. The
MTC20454 provides programmable low pass fil-
ters for each of the two channels and automatic
gain control for four individual ADSL modems.
The pipeline ADC architecture provides 13 bit dy-
namic range and a signal bandwidth of 1.1 MHz.
The device consumes only 0.7 Watt in full opera-
tion of all four modems and has a power down
mode for standby.
It is housed in a compact 100 pin thin plastic quad
flat package.
QUAD INTEGRATED ADSL CMOS
ANALOG FRONT END CIRCUIT
Figure 1. Sample board layout
MTC20454
PIN DESCRIPTION
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MTC20454
PIN DESCRIPTION (continued)
MTC20454
Figure 2. MTC20454 Grounding and Decoupling Networks
Figure 3. PIN CONNECTION
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MTC20454
ABSOLUTE MAXIMUM RATINGSOperation of the device beyond these limits may cause permanent damage. It is not implied that more than
one of these conditions can be applied simultaneously.
OPERATING CONDITIONSUnless specified, the characteristic limits of ‘Static characteristics’ in this document apply for the following
operating conditions:
ELECTRICAL CHARACTERISTICS
Static Characteristicsa. Digital Inputs
Schmitt-trigger inputs: TXi, CTRLIN, CLKIN, RESETN, TEST
Clock Driver Input b. Digital Outputs
Hard driven outputs: RXi, CLKWD, LiGPi, LiDRVi, LiDRVSD
Clock Driver Output
MTC20454
Clock Driver Output CLKM
FUNCTIONAL DECRIPTIONThe MTC20454 performs the analog portions of four ATU-C modems.
It has filters (with a programmable cut-off frequency) that use automatic continuous time tuning to avoid
time varying phase characteristics which can be of dramatic consequence for DMT modems. It requires
few external components, uses a 3.3 V supply and is packaged in a 100 pins TQFP in order to reduce
PCB area.
The following descriptions apply to each of the four analog front ends in the chip:
The Receiver (RX)The DMT signal coming from the lines to the MTCMTC20454MTC2045420454 is first filtered by the two
following external filters: POTS HP filter: Attenuation of speech and POTS signalling. Channel filter: Attenuation of echo signal to improve RX dynamic.
The signal is amplified by a low noise gain stage (-15..+31 dB) then lowpass filtered to avoid anti-aliasing
and to ease further digital processing by removing unwanted high frequency out-of-band noise. A 12 bits
A/D converter samples the data at 8.832 MS/s, transforms the signal into a igital representation and sends
it to the DMT signal processor via the multiplexed digital interface.
The Transmitter (TX/TXE)The 12 bits data at 8.832 Ms coming from the DMT signal processor through the multiplexed digital inter-
face are transformed by a D/A converter into an analog signal. This signal is then filtered to decrease DMT
sidelobes levels and meet the ANSI transmitter spectral response but also to reduce he out-of-band noise
(which can be echoed to the RX path) to an acceptable level. The pre-driver buffers The signal for the
external line driver and case of short loops provide attenuation provision
The Digital InterfaceThe digital part of the MTC20454 can be divided into two parts: The data interface converts the multiplexed data from/to the DMT signal processor into a valid
representation for the TX DAC and RX ADC for the requested line. The control interface allows the board processor to configure the MTC20454 paths (RX/TX gains, filter
band, ...) or settings.
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MTC20454
ANALOG TX/RX SIGNALSThe reference impedance for all power calculations is 100 Ohm.
DMT SignalA DMT signal is basically the sum of N independently QAM modulated signals, each carried over a distinct
carrier. The frequency separation of each carrier is 4.3125 KHz with a total number of 256 carriers (ANSI).
For a large N, the signal can be modelled by a gaussian process with a certain amplitude probability den-
sity function. Since the maximum amplitude is expected to arise very rarely, the signal is clipped to trade-
off the resulting SNR loss against AD/DA dynamic range.
A clipping factor (Vpeak/Vrms = “crest factor”) of 5 is used resulting in a maximum SNR of 75 dB. ADSL
DMT signals are nominally sent at -40 dBm/Hz +/- 3 dB (-3.65 dBm/carrier) with a maximal power of 100
mW for downlink transmitter and 4.5 mW for uplink transmitter. The minimum SNR+D needed for DMT
carrier demodulation is about (3*N+20) dB with a minimum of 38 dB where N is the constellation size of a
carrier (in bits).
Block DiagramThe transformer has a 1:2 ratio. The termination resistors are 12.5 Ohm in case of 100 Ohm lines. The
hybrid bridge resistors should be < 2.5 kOhm for low-noise. An HP filter must be used on the TX path to
reduce DMT sidelobes and out-of- band noise influence on the receiver. On the RX path, a LP filter must
be used in order to reduce the echo signal level and to avoid saturation of the input stage of the receiver.
The POTS filter is used in both directions to reduce cross talk between ADSL signals and POTS speech
and signalling.
Figure 4. AFE Block Diagram (for detailed schematics see MTB20450-EBC reference design.)
MTC20454
MTC20454RX PATH
Speech FilterAn external bi-directional LP filter for up and downstream POTS service splits out the speech signal to the
analog telephone. The ADSL analog front end integrated circuit does not contain any circuitry for the
POTS service but guarantees that the POTS bandwidth is not disturbed by spurious signals from the
ADSL spectrum.
Channel FiltersThe purpose of these external analog circuits is to provide partial echo cancellation by analog filtering of
the receive. This is feasible because the upstream and the downstream data can be modulated on sepa-
rate carriers (FDM).
Signal Attenuator (ATT) and Low Noise AmplifierThe attenuator needs to be DC decoupled from the external circuitry.
In fact, it is also used to internally fix the LNA input common mode voltage at the nominal value: AVDD/2.
This is done by the use of an internal biasing circuit. It is therefore mandatory to de-couple the MTC20454
input from any external DC biasing system. The Low Noise Amplifier (LNA) placed after the ATT will be
used in combination with the attenuation block.
The goal is to obtain a range of RX path input level varying from –15 dB to 31 dB, while maintaining the
noise contribution negligible.
RX FiltersThe combination of the external filter (an LC ladder filter typically) with the integrated low pass filter pro-
vides: echo reduction to improve dynamic Range - DMT sidelobe and out of band (anti-aliasing) attenuation. Anti alias filter (60 dB rejection @ image freq.)
Linearity of RXLinearity of the RX analog path is defined by the IM3 product of two sinusoidal signals with frequencies f1
and f2 and each with 0.5 Vpd amplitude (total _1 Vpd) at the output of the RX-AGC amplifier (i.e: before
the ADC) for the case of minimal AGC setting.
Figure 5. Signal Attenuator (ATT) and Low Noise Amplifier
