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MTC20154-TQ-C2-MTC20154-TQ-C2TR-MTC20154TQ-C2TR
Integrated ADSL CMOS Analog Front-End Circuit
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MTC20154February 2004
Features Fully integrated AFE for ADSL Overall 12 bit resolution, 1.1MHz signal
bandwidth 8.8 MS/s ADC 8.8 MS/s DAC THD: -60 dB @ full scale 1V full scale input Differential analog I/O Accurate continuous-time channel filtering3rd & 4th order tunable continuous time LP
Filters 64 pin TQFP package 350mW power consumption
Applications ADSL Front-end for all full rate and Lite
standards
DESCRIPTIONThe MTC20154 is the fifth generation Analog
Front End (AFE) designed for DMT based ADSL
(Asynchronous Digital Subscriber Line) modems
compliant with ANSI T1.413 category 2 standard.
It includes one 12 bit DAC and one 13 bit ADC.It is
intended to be used with the MTC20156/
MTC20147 DMT/ATM processors as part of the
MTK20150/MTK20141 chipsets, but may also be
used to support other xDSL signal processors.
The MTC20154 provides programmable low pass
filters for each of the two channels and automatic
gain control. A configuration pin allows the filters to
be switched from ATU-R mode to ATU-C mode.
The pipeline ADC architecture provides 13 bit dy-
namic range and a signal bandwith of 1.1 MHz.
The device consumes only 0.35 Watt in full opera-
tion and has a power down mode for standby. It is
housed in a compact 64 pin thin plastic quad flat
package.
INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT
Figure 1. Block Diagram
MTC20154
Functional DescriptionThe MTC20154 chip can be used on the ATU-C side (LT), and on the ATU-R (NT) side (defined by LTNT
pin). The selection consists mainly of a filter interchange between the RX and TX path. The filters (with a
programmable cutoff frequency) use automatic continuous time tuning to avoid time varying phase char-
acteristics which can be of dramatic consequence for DMT modems. It requires few external components,
uses a 3.3 V supply and is packaged in a 64 pins TQFP in order to reduce PCB area.
The Receiver (RX)The DMT signal coming from the line to the MTC20154 is first filtered by the two following external filters: POTS HP filter: Attenuation of speech and POTS signalling. Channel filter: Attenuation of echo signal to improve RX dynamic.
The signal is amplified by a low noise gain stage (-15..+31 dB) then low-pass filtered to avoid anti-aliasing
and to ease further digital processing by removing unwanted high frequency out-of-band noise.
A 12 bits A/D converter samples the data at 8.832 MS/s, transforms the signal into a digital representation
and sends it to the DMT signal processor via the digital interface.
The Transmitter (TX/TXE)The 12 bits data at 8.832 Ms coming from the DMT signal processor through the digital interface are trans-
formed by a D/A converter into an analog signal. This signal is then filtered to decrease DMT sidelobes
levels and meet the ANSI transmitter spectral response but also to reduce the out-of-band noise (which
can be echoed to the RX path) to an acceptable level. The pre-driver buffers the signal for the external
line driver and in case of short loops provide attenuation provision (-9..+6 dB).
The VCXOThe VCXO is divided in a XTAL driver and an auxilliary 8 bits DAC for timing recovery.
The XTAL driver is able to operate at 35.328 MHz or 17.664 MHz. An internal PLL will be used to double
the frequency in the 17.664 MHz case. It also provides an amplitude regulation mechanism to avoid tem-
perature/-supply/technology dependent frequency pulling.
The DAC which is driven by the CTRLIN pin provides a current output with 8 bits resolution and can be
used to tune the XTAL frequency with the help of external components. A time constant between DAC
input and VCXO output can be introduced (via the CTRLIN interface) and programmed with the help of an
external capacitor (on VCOCAP pin).
The Digital InterfaceThe digital part of the MTC20154 can be divided into two parts: The data interface converts the multiplexed
data from/to the DMT signal processor into a valid representation for the TX DAC and RX ADC. The con-
trol interface allows the board processor to configure the MTC20154 paths (RX/TX gains, filter band, ...)
or settings.
PackageThe MTC20154 is housed in a 64-pin TQFP package.
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MTC20154
Pin Assignement
Table 1. Pinning Description MTC20154 AFE
MTC20154
Table 1. Pinning Description MTC20154 AFE (continued)
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MTC20154
Figure 2. MTC20154 Grounding and Decoupling Networks
Table 1. Pinning Description MTC20154 AFE (continued)
MTC20154
Figure 3. Pin connection (Top view)
ELECTRICAL RATINGS AND CHARACTERISTICS
Absolute Maximum RatingsOperation of the device beyond these limits may cause permanent damage. It is not implied that more than
one of these conditions can be applied simultaneously.
Table 2. Electrical Characteristics
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MTC20154
Operating ConditionsUnless specified, the characteristic limits of ’Static characteristics’ in this document apply for the following
operating conditions:
Table 3. Operating conditions
Static Characteristics
Digital InputsSchmitt-trigger inputs: TXi, CTRLIN, PDOWN, LTNT, RESETN, TEST
Table 4. Digital Inputs
Digital OutputsHard driven outputs: RXi, CLKWD, GPI, DRVI, DRVSD
Table 5. Digital OutputsClock Driver output: CLKM
Table 6. Clock Driver output
MTC20154
Analog TX/RX SignalsThe reference impedance for all power calculations is 100Ω.
DMT SignalA DMT signal is basically the sum of N independently QAM modulated signals, each carried over a distinct
carrier. The frequency separation of each carrier is 4.3125 KHz with a total number of 256 carriers (ANSI).
For large N, the signal can be modelled by a gaussian process with a certain amplitude probability density
function. Since the maximum amplitude is expected to arise very rarely, the signal is clipped to trade-off
the resulting SNR loss against AD/DA dynamic range.
A clipping factor (Vpeak/Vrms = ”crest factor”) of 5 is used resulting in a maximum SNR of 75 dB. ADSL
DMT signals are nominally sent at -40 dBm/Hz +/- 3 dB (-3.65 dBm/carrier) with a maximal power of 100
mW for downlink transmitter and 4.5 mW for uplink transmitter.
The minimum SNR+D needed for DMT carrier demodulation is about (3*N+20) dB with a minimum of 38
dB where N is the constellation size of a carrier (in bits).
Table 7. Signal Levels (on the line)
Table 8. Total Signal Level (on the line)
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MTC20154
ATU-C Side Block DiagramThe transformer at the ATU-C side has a 1:2 ratio. The termination resistors are 12.5Ω in case of 100Ω
lines. The hybrid bridge resistors should be < 2.5 kΩ for low-noise.
An HP filter must be used on the TX path to reduce DMT sidelobes and out-of-band noise influence on the
receiver.
On the RX path, a LP filter must be used in order to reduce the echo signal level and to avoid saturation
of the input stage of the receiver.
The POTS filter is used in both directions to reduce crosstalk between ADSL signals and POTS speech
and signalling.
Figure 4. ATU-C AFE Schematics (For detailed schematics see MTB-20150-EBC reference design.)
MTC20154
ATU-R Side Block DiagramThe ATU-R side block diagram is equal to the ATU-C side block diagram with the following differences:
- The transformer ratio is 1:1
- Termination resistors are 50Ω for 100Ω lines.
An LP filter may be used on the TX path to reduce DMT sidelobes and out-of-band noise influence on the
receiver.
On the RX path, a HP filter must be used in order to reduce the echo signal level and to avoid saturation
of the input stage of the receiver.
The POTS filter is used in both directions to reduce crosstalk between ADSL signals and POTS speech
and signalling.
Figure 5. ATU-R AFE Schematics (For detailed schematics see MTB-20141-EBR reference design.)
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MTC20154
MTC20154 RX PATH
Speech FilterAn external bidirectional LP filter for up and downstream POTS service splits out the speech signal to the
analog telephone circuit on both the NT and LT sides of the line. The ADSL analog front end integrated
circuit does not contain any circuitry for the POTS service but guarantees that the POTS bandwidth is not
disturbed by spurious signals from the ADSL spectrum.
Channel FiltersThe purpose of these external analog circuits is to provide partial echo cancellation by analog filtering of
the receive signal for both ATU-R (reception of downstream channel) and ATU-C (reception of upstream
channel). This is feasible because the upstream and the downstream data can be modulated on separate
carriers (FDM).
Signal Attenuator (ATT) and Low Noise AmplifierThe attenuator needs to be DC decoupled from the external circuitry. In fact, it is also used to internally fix
the LNA input common mode voltage at the nominal value: AVDD/2. This is done by the use of an internal
biasing circuit. It is therefore mandatory to decouple the MTC20154 input from any external DC biasing
system. The Low Noise Amplifier (LNA) placed after the ATT will be used in combination with the attenu-
ation block. The goal is to obtain a range of RX path input level varying from –15 dB to 31 dB, while main-
taining the noise contribution negligible.
Figure 6. Signal Attenuator (ATT) and Low Noise Amplifier
The input attenuator will have the following characteristics
Table 9. Attenuator Characteristics
