MPC970FA ,Low voltage PLL clock driver**SEMICONDUCTOR TECHNICAL DATA ** * ** * ** The MPC970 is a 3.3V compatible, PLL based clock ..
MPC972 ,LOW VOLTAGE PLL CLOCK DRIVERfeatures an extensive level of frequencyprogrammability between the 12 outputs as well as the input ..
MPC972FA ,Low voltage PLL clock driverfeatures an extensive level of frequencyprogrammability between the 12 outputs as well as the input ..
MPC973 ,LOW VOLTAGE PLL CLOCK DRIVERfeatures an extensive level of frequencyprogrammability between the 12 outputs as well as the input ..
MPC973 ,LOW VOLTAGE PLL CLOCK DRIVERfeatures an extensive level of frequencyprogrammability between the 12 outputs as well as the input ..
MPC973 ,LOW VOLTAGE PLL CLOCK DRIVERfeatures an extensive level of frequencyprogrammability between the 12 outputs as well as the input ..
MSP430F148IPMR ,16-Bit Ultra-Low-Power Microcontroller, 48 kB Flash, 2KB RAM, 12 bit ADC, 2 USARTs, HW multiplier SLAS272F − JULY 2000 − REVISED JUNE 2004 ..
MSP430F148IRTDR ,16-Bit Ultra-Low-Power Microcontroller, 48 kB Flash, 2KB RAM, 12 bit ADC, 2 USARTs, HW multiplier SLAS272F − JULY 2000 − REVISED JUNE 2004 ..
MSP430F148IRTDT ,16-Bit Ultra-Low-Power Microcontroller, 48 kB Flash, 2KB RAM, 12 bit ADC, 2 USARTs, HW multiplier SLAS272F − JULY 2000 − REVISED JUNE 2004 ..
MSP430F149 ,16-Bit Ultra-Low-Power Microcontroller, 60 kB Flash, 2KB RAM, 12 bit ADC, 2 USARTs, HW multiplier SLAS272F − JULY 2000 − REVISED JUNE 2004 ..
MSP430F1491IPM ,16-Bit Ultra-Low-Power Microcontroller, 60 kB Flash, 2KB RAM, 2 USARTs, HW multiplier SLAS272F − JULY 2000 − REVISED JUNE 2004 ..
MSP430F1491IPM ,16-Bit Ultra-Low-Power Microcontroller, 60 kB Flash, 2KB RAM, 2 USARTs, HW multiplier SLAS272F − JULY 2000 − REVISED JUNE 2004 ..
MPC970FA
Low voltage PLL clock driver
SEMICONDUCTOR TECHNICAL DATA - - -
The MPC970 is a 3.3V compatible, PLL based clock driver devices
targeted for high performance RISC or CISC processor based systems. Fully Integrated PLL Output Frequency Up to 250MHz Compatible with PowerPC and Pentium Processors Output Frequency Configuration On–Board Crystal Oscillator 52–Lead TQFP Packaging ±50ps Typical Cycle–to–Cycle Jitter
The MPC970 was designed specifically to drive today’s PowerPC 601
and Pentium processors while providing the necessary performance to
address higher frequency PowerPC 601 as well as PowerPC 603 and
PowerPC 604 applications. The 2x_PCLK output can toggle at up to
250MHz while the remaining outputs can be configured to drive the other
system clocks for MPC 601 based systems. As the processor based
clock speeds increase the processor bus will likely run at one third or
even one fourth the processor clock. The MPC970 supports the
necessary waveforms to drive the BCLKEN input signal of the MPC 601
when the processor bus is running at a lower frequency than the
processor. The MPC970 uses an advanced PLL design which minimizes
the jitter generated on the outputs. The jitter specification is well within the
requirements of the Pentium processor and meets the stringent
preliminary specifications of the PowerPC 603 and PowerPC 604
processors. The application section of this data sheet deals in more detail
with driving PowerPC and Pentium processor based systems.
The external feedback option of the MPC970 provides for a near zero delay between the reference clock input and the outputs
of the device. This feature is required in applications where a master clock is being picked up off the backplane and regenerated
and distributed on a daughter card. The advanced PLL of the MPC970 eliminates the dead zone of the phase detector and
minimizes the jitter of the PLL so that the phase error variation is held to a minimum. This phase error uncertainty makes up a
major portion of the part–to–part skew of the device.
For single clock driver applications the MPC970 provides an internal oscillator and internal feedback to simplify board layout
and minimize system cost. By using the on–board crystal oscillator the MPC970 acts as both the clock generator and distribution
chip. The external component is a relatively inexpensive crystal rather than a more expensive oscillator. Since in single board
applications the delay between the input reference and the outputs is inconsequential an internal feedback option is offered. The
internal feedback simplifies board design in that the system designer need not worry about noise being coupled into the feedback
line due to board parasitics and layout. The internal feedback is a fixed divide by 32 of the VCO. This divide ratio ensures that the
input crystals will be ≤20MHz, thus keeping the crystal costs down and ensuring availability from multiple vendors.
