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SST39VF020-90-4C-WH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF020-90-4I-NH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF020-90-4I-WH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF040 , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF040-70-4C-NH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39VF040-70-4C-NH , 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
MPC5200BV400-MPC5200CBV266-MPC5200CBV400-SPC5200CBV400
MPC5200 Hardware Specifications
NOTE: The information in this document is subject to
change. For the latest data on the MPC5200, visit
www.mobilegt.com and proceed to the MPC5200
Product Summary Page.
OverviewThe MPC5200 integrates a high performance MPC603e series G2_LE core with a
rich set of peripheral functions focused on communications and systems
integration. The G2_LE core design is based on the PowerPC® core architecture.
MPC5200 incorporates an innovative BestComm I/O subsystem, which isolates
routine maintenance of peripheral functions from the embedded G2_LE core. The
MPC5200 contains a SDRAM/DDR Memory Controller, a flexible External Bus
Interface, PCI Controller, USB, ATA, Ethernet, six Programmable Serial Controllers
(PSC), I2 C, SPI, CAN, J1850, Timers, and GPIOs.
2FeaturesKey features are shown below. MPC603e series G2_LE core Superscalar architecture 760 MIPS at 400 MHz (-40 to +85 oC) 16 k Instruction cache, 16 k Data cache Double precision FPU Instruction and Data MMU Standard and Critical interrupt capability SDRAM / DDR Memory Interface up to 132-MHz operation SDRAM and DDR SDRAM support 256-MByte addressing range per CS, two CS available 32-bit data bus Built-in initialization and refresh Flexible multi-function External Bus Interface Supports interfacing to ROM/Flash/SRAM memories or other memory
mapped devices
Topic Page Overview ......................................1 Features .......................................1 Electrical and Thermal
Characteristics..............................5 Package Description ..................60 System Design Information ........69 Ordering Information ..................74 Document Revision History........75
Freescale Semiconductor, Inc.
