MPC2605ZP66 ,Integrated Secondary Cache for PowerPC Microprocessors**Order this documentby MPC2605/DSEMICONDUCTOR TECHNICAL DATAMPC2605Product PreviewIntegrated Secon ..
MPC506AP ,16-Channel Single-Ended Input Analog MultiplexerPIN CONFIGURATIONTop ViewTop View28 Out 28 Out A+V 1 +V 1SUPPLY SUPPLY –V27 –V Out B 2 27NC 2 SUPPL ..
MPC506APG4 , 16-Channel Single-Ended Input Analog MultiplexerELECTRICAL CHARACTERISTICSSupplies = +15V, –15V; V (Pin 13) = Open; V (Logic Level High) = +4.0V; V ..
MPC506AU ,16-Channel Single-Ended Input Analog MultiplexerPIN CONFIGURATIONTop ViewTop View28 Out 28 Out A+V 1 +V 1SUPPLY SUPPLY –V27 –V Out B 2 27NC 2 SUPPL ..
MPC506AU/1K ,16-Channel Single-Ended Input Analog MultiplexerMPC506MPC507MPC506AMPC507ASBFS018A – JANUARY 1988 – REVISED OCTOBER 2003Single-Ended 16-Channel/Dif ..
MPC506AUG4 ,16-Channel Single-Ended Input Analog Multiplexer 28-SOIC -40 to 85ELECTRICAL CHARACTERISTICSSupplies = +15V, –15V; V (Pin 13) = Open; V (Logic Level High) = +4.0V; V ..
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MPC2605ZP66
Integrated Secondary Cache for PowerPC Microprocessors
Product Preview
Integrated Secondary Cache
for PowerPC MicroprocessorsThe MPC2605 is a single chip, 256KB integrated look–aside cache with
copy–back capability designed for PowerPC applications (MPC603 and
MPC604). Using 0.38 μm technology along with standard cell logic technology,
the MPC2605 integrates data, tag, host interface, and least recently used (LRU)
memory with a cache controller to provide a 256KB, 512KB, or 1 MB Level 2
cache with one, two, or four chips on a 64–bit PowerPC bus. Single Chip L2 Cache for PowerPC 66 MHz Zero Wait State Performance (2–1–1–1 Burst) Four–Way Set Associative Cache Design 32K x 72 Data Memory Array 8K x 18 Tag Array Address Parity Support LRU Cache Control Logic Copy–Back or Write–Through Modes of Operation Copy–Back Buffer for Improved Performance Single 3.3 V Power Supply 5 V Tolerant I/O One, Two, or Four Chip Cache Solution (256KB, 512KB, or 1MB) Single Clock Operation Compliant with IEEE Standard 1149.1 Test Access Port (JTAG) Supports up to Four Processors in a Shared Cache Configuration High Board Density 25 mm 241 PBGA Package
DH0 – DH31
DL0 – DL31
DP0 – DP7
A0 – A31
60X BUS
INTERFACE
BLOCK DIAGRAMCONTROL
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
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SEMICONDUCTOR TECHNICAL DATA
