MM74HCT08MX ,Quad 2-Input AND GateMM74HCT08 Quad 2-Input AND GateDecember 1983Revised January 2005MM74HCT08Quad 2-Input AND Gate
MM74HCT08N ,Quad 2-Input AND GateMM74HCT08 Quad 2-Input AND GateDecember 1983Revised January 2005MM74HCT08Quad 2-Input AND Gate
MM74HCT08SJ ,Quad 2-Input AND GateFeaturesThe MM74HCT08 is a logic function fabricated by using
MM74HCT08M-MM74HCT08MTC-MM74HCT08MTCX-MM74HCT08MX-MM74HCT08N-MM74HCT08SJ-MM74HCT08SJX
Quad 2-Input AND Gate
MM74HCT08 Quad 2-Input AND Gate December 1983 Revised January 2005 MM74HCT08 Quad 2-Input AND Gate General Description Features The MM74HCT08 is a logic function fabricated by usingTTL, LS pin-out and threshold compatible advanced silicon-gate CMOS technology which providesFast switching: t , t = 12 ns (typ) PLH PHL the inherent benefits of CMOS—low quiescent power and Low power: 10 μW at DC wide power supply range. This device is input and output High fan-out, 10 LS-TTL loads characteristic and pinout compatible with standard 74LS logic families. All inputs are protected from static discharge damage by internal diodes to V and ground. CC MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. Ordering Code: Package Order Number Package Description Number MM74HCT08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HCT08MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HCT08SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HCT08MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HCT08N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Diagram Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP © 2005 DS005754
