MM74HC86M ,Quad 2-Input Exclusive OR GateFeaturesThe MM74HC86 EXCLUSIVE OR gate utilizes advanced
MM74HC86M-MM74HC86MTC-MM74HC86MTCX-MM74HC86MX-MM74HC86N-MM74HC86SJ
Quad 2-Input Exclusive OR Gate
MM74HC86 Quad 2-Input Exclusive OR Gate September 1983 Revised January 2005 MM74HC86 Quad 2-Input Exclusive OR Gate General Description Features The MM74HC86 EXCLUSIVE OR gate utilizes advancedTypical propagation delay: 9 ns silicon-gate CMOS technology to achieve operatingWide operating voltage range: 2–6V speeds similar to equivalent LS-TTL gates while maintain- Low input current: 1 μA maximum ing the low power consumption and high noise immunity Low quiescent current: 20 μA maximum (74 Series) characteristic of standard CMOS integrated circuits. These gates are fully buffered and have a fanout of 10 LS-TTLOutput drive capability: 10 LS-TTL loads loads. The 74HC logic family is functionally as well as pin out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to V and ground. CC Ordering Code: Package Order Number Package Description Number MM74HC86M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC86MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC86SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC86MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC86N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74HC86NX_NL N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Truth Table Inputs Outputs Pin Assignments for DIP, SOIC, SOP and TSSOP AB Y LL L LH H HL H HH L Y = A ⊕ B = A B + AB Top View © 2005 DS005305
