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MM74HC76N
Dual J-K Flip-Flops with Preset and Clear
TL/F/5074
MM54HC76/MM74HC76
Dual
J-K
Flip-Flops
with
Preset
and
Clear
January 1988
MM54HC76/MM74HC76 Dual J-K Flip-Flops
with Preset and Clear
General Description
These high speed(30 MHz minimum)J-K Flip-Flops utilize
advancedsilicon-gateCMOS technology toachieve,thelow
power consumption and high noise immunityof standard
CMOS integrated circuits, along withthe abilityto drive10
LS-TTL loads.
Each flip-flophas independentJ,K, PRESET, CLEAR,and
CLOCK inputs andQ andQ outputs. These devicesare
edge sensitivetothe clock inputand change stateonthe
negative going transitionofthe clock pulse. Clearandpre-
setareindependentofthe clockand accomplishedbyalow
logic levelonthe corresponding input.
The 54HC/74HC logic familyis functionallyas wellaspin-
out compatible withthe standard 54LS/74LS logic family.
All inputsare protected from damage dueto static dis-
chargeby internal diode clampsto VCCand ground.
Features Typical propagation delay:16ns Wide operating voltage range Low input current:1mA maximum Low quiescent current:40mA maximum (74HC Series) High output drive:10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
TL/F/5074–1
Top View
Order Number MM54HC76or MM74HC76
Truth Table
Inputs Outputs CLR CLK J L Q Q X X X H L X X X L H X X X L* L* v L L Q0 Q0 v HL H L v LH L H v H H TOGGLE H X X Q0 Q0
*Thisisan unstablecondition,andisnot guaranteed
TL/F/5074–2of2)
TL/F/5074–3
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
