MM74HC74AMX ,Dual D-Type Flip-Flop with Preset and ClearMM74HC74A Dual D-Type Flip-Flop with Preset and ClearSeptember 1983Revised January 2005MM74HC74ADua ..
MM74HC74AN ,Dual D-Type Flip-Flop with Preset and ClearMM74HC74A Dual D-Type Flip-Flop with Preset and ClearSeptember 1983Revised January 2005MM74HC74ADua ..
MM74HC74ASJ ,Dual D-Type Flip-Flop with Preset and ClearFeaturesgrated circuits, along with the ability to drive 10 LS-TTLloads.
MM74HC74AM-MM74HC74AMTC-MM74HC74AMTCX-MM74HC74AMX-MM74HC74AN-MM74HC74ASJ-MM74HC74ASJX
Dual D-Type Flip-Flop with Preset and Clear
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear September 1983 Revised January 2005 MM74HC74A Dual D-Type Flip-Flop with Preset and Clear The 74HC logic family is functionally and pinout compatible General Description with the standard 74LS logic family. All inputs are protected The MM74HC74A utilizes advanced silicon-gate CMOS from damage due to static discharge by internal diode technology to achieve operating speeds similar to the clamps to V and ground. CC equivalent LS-TTL part. It possesses the high noise immu- nity and low power consumption of standard CMOS inte- Features grated circuits, along with the ability to drive 10 LS-TTL loads.Typical propagation delay: 20 ns This flip-flop has independent data, preset, clear, and clockWide power supply range: 2–6V inputs and Q and Q outputs. The logic level present at the Low quiescent current: 40 μA maximum (74HC Series) data input is transferred to the output during the positive- Low input current: 1 μA maximum going transition of the clock pulse. Preset and clear are Fanout of 10 LS-TTL loads independent of the clock and accomplished by a low level at the appropriate input. Ordering Code: Package Order Number Package Description Number MM74HC74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC74AMX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC74ASJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC74AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC74AMTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Truth Table Pin Assignments for DIP, SOIC, SOP and TSSOP Inputs Outputs PR CLR CLK D Q Q LH X X H L HL X X L H L L X X H (Note 1) H (Note 1) HH ↑ HH L HH ↑ LL H HH L X Q0 Q 0 Note: Q0 = the level of Q before the indicated input conditions were estab- lished. Note 1: This configuration is nonstable; that is, it will not persist when pre- set and clear inputs return to their inactive (HIGH) level. © 2005 DS005106
