MM74HC597MX ,8-Bit Shift Registers with Input LatchesBlock Diagram (Positive Logic)Timing Diagram 2MM74HC597MM74HC597Absolute Maximum Ratings(Note 2) R ..
MM74HC597MX ,8-Bit Shift Registers with Input LatchesFeaturesThis high speed register utilizes advanced silicon-gate
MM74HC597M-MM74HC597MX-MM74HC597N
8-Bit Shift Registers with Input Latches
MM74HC597 8-Bit Shift Registers with Input Latches January 1988 Revised January 2004 MM74HC597 8-Bit Shift Registers with Input Latches General Description Features This high speed register utilizes advanced silicon-gate8-bit parallel storage register inputs CMOS technology. It has the high noise immunity and lowWide operating voltage range: 2V–6V power consumption of standard CMOS integrated circuits, Shift register has direct overriding load and clear as well as the ability to drive 10 LS-TTL loads. Guaranteed shift frequency: DC to 30 MHz The MM74HC597 comes in a 16-pin package and consists Low quiescent current: 80 μA maximum of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift regis- ter have positive-edge triggered clocks. the shift register also has direct load (from storage) and clear inputs. The 74HC logic family is speed, function, and pin-out com- patible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to V and ground. CC Ordering Code: Order Number Package Number Package Description MM74HC597M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow (Note 1) MM74HC597SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC597N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table RCK SCK SLOAD SCLR Function ↑ X X X Data Loaded to input latches Data loaded from inputs to ↑ XL H shift register No Data transferred from clock X L H input latches to shift edge register Invalid logic, state of XX L L shift register indeterminate when signals removed X X H L Shift register cleared Shift register clocked X ↑ HH Q = Q −1, Q = SER n n 0 Top View © 2004 DS005343
