MM74HC594M ,8-Bit Shift Register with Output RegistersFeaturesloads. Low quiescent current: 80 μA maximumThis device contains an 8-bit serial-in, paralle ..
MM74HC595 ,8-Bit Shift Registers with Output LatchesFeaturesThe MM74HC595 high speed shift register utilizes
MM74HC594M
8-Bit Shift Register with Output Registers
MM74HC594 8-Bit Shift Register with Output Registers January 1992 Revised May 1999 MM74HC594 8-Bit Shift Register with Output Registers The 74HC logic family is speed, function, and pin-out com- General Description patible with the standard 74LS logic family. All inputs are This high speed shift register utilizes advanced silicon-gate protected from damage due to static discharge by internal CMOS technology. This device possesses the high noise diode clamps to V and ground. CC immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL Features loads. � Low quiescent current: 80 μA maximum This device contains an 8-bit serial-in, parallel-out shift reg- ister that feeds an 8-bit D-type storage register. Separate � Low input current: 1 μA maximum clocks and direct overriding clears are provided for both the � 8-bit serial-in, parallel-out shift register with storage shift register and the storage register. The shift register has � Wide operating voltage range: 2V to 6V a direct-overriding clear, serial input, and serial output � Cascadable (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both � Shift register has direct clear clocks are connected together, the shift register state will � Guaranteed shift frequency: DC to30 MHz always be one clock pulse ahead of the storage register. Ordering Code: Order Number Package Number Package Description MM74HC594M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow MM74HC594N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table RCK SCK SCLR RCLR Function X X X L Storage Register cleared Shift Register cleared XX L X Q’ = 0 H Shift Register clocked X ↑ HH Q = Q , Q = SER N n−1 0 Contents of Shift ↑ XH H Register transferred to output latches © 1999 DS010915.prf
