MM74HC589N ,8-Bit Shift Registers with Input Latches and 3-STATE Serial OutputMM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial OutputSeptember 1983Revised S ..
MM74HC589N ,8-Bit Shift Registers with Input Latches and 3-STATE Serial OutputBlock Diagram (positive logic) 2MM74HC589MM74HC589Absolute Maximum Ratings(Note 1) Recommended Ope ..
MM74HC58N , Dual AND-OR-Invert Gate / Dual AND-OR Gate
MM74HC594M ,8-Bit Shift Register with Output RegistersFeaturesloads. Low quiescent current: 80 μA maximumThis device contains an 8-bit serial-in, paralle ..
MM74HC595 ,8-Bit Shift Registers with Output LatchesFeaturesThe MM74HC595 high speed shift register utilizes
MM74HC589M-MM74HC589N
8-Bit Shift Registers with Input Latches and 3-STATE Serial Output
MM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output September 1983 Revised September 2001 MM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output General Description Features The MM74HC589 high speed shift register utilizes8-bit parallel storage register inputs advanced silicon-gate CMOS technology to achieve theWide operating voltage range: 2V–6V high noise immunity and low power consumption of stan- Shift register has direct overriding load dard CMOS integrated circuits, as well as the ability to Guaranteed shift frequency. . . DC to 30 MHz drive 15 LS-TTL loads. Low quiescent current: 80 μA maximum (74HC Series) The MM74HC589 comes in a 16-pin package and consists 3-STATE output for ‘Wire-OR' of an 8-bit storage latch feeding a parallel-in, serial-out 8- bit shift register. Data can also be entered serially the shift register through the SER pin. Both the storage register and shift register have positive-edge triggered clocks, RCK and SCK, respectively. SLOAD pin controls parallel LOAD or serial shift operations for the shift register. The shift register has a 3-STATE output to enable the wire-ORing of multiple devices on a serial bus. The 74HC logic family is speed, function, and pin-out com- patible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to V and ground. CC Ordering Code: Order Number Package Number Package Description MM74HC589M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC589SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC589N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table RCK SCK SLOAD OE Function XX X HQ in Hi-Z State H XX X LQ is enabled H ↑ X X X Data loaded into input latches ↑ X L X Data loaded into shift register from pins H or L X L X Data loaded from latches to shift register Top View X ↑ H X Shift register is shifted. Data on SER pin is shifted in. ↑↑ H X Data is shifted in shift register, and data is loaded into latches © 2001 DS005368
