MM74HC573SJX ,3-STATE Octal D-Type LatchFeaturesally suited for interfacing with bus lines in a bus organizedsystem.
MM74HC573MTC-MM74HC573MTCX-MM74HC573N-MM74HC573SJX-MM74HC573WM-MM74HC573WMX
3-STATE Octal D-Type Latch
MM74HC573 3-STATE Octal D-Type Latch September 1983 Revised May 2000 MM74HC573 3-STATE Octal D-Type Latch of what signals are present at the other inputs and the state General Description of the storage elements. The MM74HC573 high speed octal D-type latches utilize The 74HC logic family is speed, function and pinout com- advanced silicon-gate P-well CMOS technology. They pos- patible with the standard 74LS logic family. All inputs are sess the high noise immunity and low power consumption protected from damage due to static discharge by internal of standard CMOS integrated circuits, as well as the ability diode clamps to V and ground. CC to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ide- Features ally suited for interfacing with bus lines in a bus organized system. Typical propagation delay: 18 ns When the LATCH ENABLE(LE) input is HIGH, the Q out- Wide operating voltage range: 2 to 6 volts puts will follow the D inputs. When the LATCH ENABLE Low input current: 1 μA maximum goes LOW, data at the D inputs will be retained at the out- Low quiescent current: 80 μA maximum (74HC Series) puts until LATCH ENABLE returns HIGH again. When a HIGH logic level is applied to the OUTPUT CONTROL OCCompatible with bus-oriented systems input, all outputs go to a HIGH impedance state, regardless Output drive capability: 15 LS-TTL loads Ordering Code: Order Number Package Number Package Description MM74HC573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide MM74HC573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Output Latch Data Output Control Enable L HHH LH L L LL X Q 0 HX X Z H = HIGH Level L = LOW Level Q = Level of output before steady-state input conditions were established. 0 Z = High Impedance X = Don't Care Top View © 2000 DS005212
