MM74HC374SJX ,3-STATE Octal D-Type Flip-FlopFeaturesally suited for interfacing with bus lines in a bus organizedsystem. Typical propagation de ..
MM74HC374SJX ,3-STATE Octal D-Type Flip-FlopGeneral Descriptionstorage elements.The MM74HC374 high speed Octal D-Type Flip-Flops uti-The 74HC l ..
MM74HC374WM ,3-STATE Octal D-Type Flip-FlopMM74HC374 3-STATE Octal D-Type Flip-FlopSeptember 1983Revised February 1999MM74HC3743-STATE Octal D ..
MM74HC374WMX ,3-STATE Octal D-Type Flip-FlopMM74HC374 3-STATE Octal D-Type Flip-FlopSeptember 1983Revised February 1999MM74HC3743-STATE Octal D ..
MM74HC393M ,Dual 4-Bit Binary CounterFeaturesThe MM74HC393 counter circuits contain independent rip-
MM74HC374MTC-MM74HC374MTCX-MM74HC374N-MM74HC374SJX-MM74HC374WM-MM74HC374WMX
3-STATE Octal D-Type Flip-Flop
MM74HC374 3-STATE Octal D-Type Flip-Flop September 1983 Revised February 1999 MM74HC374 3-STATE Octal D-Type Flip-Flop signals are present at the other inputs and the state of the General Description storage elements. The MM74HC374 high speed Octal D-Type Flip-Flops uti- The 74HC logic family is speed, function, and pinout com- lize advanced silicon-gate CMOS technology. They pos- patible with the standard 74LS logic family. All inputs are sess the high noise immunity and low power consumption protected from damage due to static discharge by internal of standard CMOS integrated circuits, as well as the ability diode clamps to V and ground. CC to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ide- Features ally suited for interfacing with bus lines in a bus organized system. � Typical propagation delay: 20 ns These devices are positive edge triggered flip-flops. Data � Wide operating voltage range: 2–6V at the D inputs, meeting the setup and hold time require- � Low input current: 1 μA maximum ments, are transferred to the Q outputs on positive going � Low quiescent current: 80 μA maximum transitions of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all � Compatible with bus-oriented systems outputs go to a high impedance state, regardless of what � Output drive capability: 15 LS-TTL loads Ordering Code: Order Number Package Number Package Description MM74HC374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide MM74HC374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC374MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP, SOIC, SOP and TSSOP Output Clock Data Output Control L ↑ HH L ↑ LL LL X Q 0 HX X Z H = HIGH Level L = LOW Level X = Don't Care ↑ = Transition from LOW-to-HIGH Z = High Impedance State Q = The level of the output before steady state input conditions were 0 established Top View © 1999 DS005336.prf
