MM74HC373MTCX ,3-STATE Octal D-Type LatchFeaturessuited for interfacing with bus lines in a bus organized sys-tem. Typical propagation delay ..
MM74HC373MTCX ,3-STATE Octal D-Type LatchFeaturessuited for interfacing with bus lines in a bus organized sys-tem. Typical propagation delay ..
MM74HC373MTCX ,3-STATE Octal D-Type LatchGeneral Descriptionstorage elements.The MM74HC373 high speed octal D-type latches utilizeThe 74HC l ..
MM74HC373MTCX ,3-STATE Octal D-Type LatchMM74HC373 3-STATE Octal D-Type LatchSeptember 1983Revised February 1999MM74HC3733-STATE Octal D-Typ ..
MM74HC373N ,3-STATE Octal D-Type LatchMM74HC373 3-STATE Octal D-Type LatchSeptember 1983Revised February 1999MM74HC3733-STATE Octal D-Typ ..
MM74HC373SJ ,3-STATE Octal D-Type LatchElectrical CharacteristicsT = 25°CT = - 40 to 85°CT = - 55 to 125°CA A A VSymbol Parameter Conditio ..
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MN6460A ,A/D Converter for Digital Audio EquipmentFeaturesN.C. N.C.14 29EXCLK 15 28 AMPBIAS Analog and digital-mixed CMOS LSICV N.C.SS 16 27CV AV A/D ..
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MM74HC373MTC-MM74HC373MTCX-MM74HC373N-MM74HC373SJ-MM74HC373SJX-MM74HC373WM-MM74HC373WMX
3-STATE Octal D-Type Latch
MM74HC373 3-STATE Octal D-Type Latch September 1983 Revised February 1999 MM74HC373 3-STATE Octal D-Type Latch signals are present at the other inputs and the state of the General Description storage elements. The MM74HC373 high speed octal D-type latches utilize The 74HC logic family is speed, function, and pin-out com- advanced silicon-gate CMOS technology. They possess patible with the standard 74LS logic family. All inputs are the high noise immunity and low power consumption of protected from damage due to static discharge by internal standard CMOS integrated circuits, as well as the ability to diode clamps to V and ground. CC drive 15 LS-TTL loads. Due to the large output drive capa- bility and the 3-STATE feature, these devices are ideally Features suited for interfacing with bus lines in a bus organized sys- tem. � Typical propagation delay: 18 ns When the LATCH ENABLE input is HIGH, the Q outputs � Wide operating voltage range: 2 to 6 volts will follow the D inputs. When the LATCH ENABLE goes � Low input current: 1 μA maximum LOW, data at the D inputs will be retained at the outputs � Low quiescent current: 80 μA maximum (74 Series) until LATCH ENABLE returns HIGH again. When a high logic level is applied to the OUTPUT CONTROL input, all � Output drive capability: 15 LS-TTL loads outputs go to a high impedance state, regardless of what Ordering Code: Order Number Package Number Package Description MM74HC373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide MM74HC373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Output Latch Data 373 Pin Assignments for DIP, SOIC, SOP and TSSOP Control Enable Output L HHH LH L L LL X Q 0 HX X Z H = HIGH Level L = LOW Level Q = Level of output before steady-state input conditions were established. 0 Z = High Impedance Top View © 1999 DS005335.prf