MM74HC32SJX ,Quad 2-Input OR GateFeaturesThe MM74HC32 OR gates utilize advanced silicon-gate
MM74HC32M-MM74HC32MTC-MM74HC32MTCX-MM74HC32MX-MM74HC32N-MM74HC32SJX
Quad 2-Input OR Gate
MM74HC32 Quad 2-Input OR Gate September 1983 Revised January 2005 MM74HC32 Quad 2-Input OR Gate General Description Features The MM74HC32 OR gates utilize advanced silicon-gateTypical propagation delay: 10 ns CMOS technology to achieve operating speeds similar toWide power supply range: 2–6V LS-TTL gates with the low power consumption of standard Low quiescent current: 20 μA maximum (74HC Series) CMOS integrated circuits. All gates have buffered outputs Low input current: 1 μA maximum providing high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as wellFanout of 10 LS-TTL loads as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static dis- charge by internal diode clamps to V and ground. CC Ordering Code: Package Order Number Package Description Number MM74HC32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC32MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC32SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC32MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC32MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74HC32N_NL N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Logic Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Y = A + B (1 of 4) Top View © 2005 DS005132
