MM74HC194N ,4-Bit Bidirectional Universal Shift RegisterMM54HC194/MM74HC1944-BitBidirectionalUniversalShiftRegisterNovember1995MM54HC194/MM74HC1944-BitBidi ..
MM74HC221AM ,Dual Non-Retriggerable Monostable Multivibratorfeatures both a negative, A, and a posi-
MM74HC194N
4-Bit Bidirectional Universal Shift Register
TL/F/5323
MM54HC194/MM74HC194
4-Bit
Bidirectional
Universal
Shift
Register
November 1995
MM54HC194/MM74HC194
4-Bit Bidirectional Universal Shift Register
General Description
This 4-bit high speed bidirectional shift register utilizesad-
vanced silicon-gate CMOS technologyto achievethelow
power consumption and high noise immunityof standard
CMOS integrated circuits, along withthe abilityto drive10
LS-TTL loads. This device operatesat speeds similartothe
equivalentlow power Schottky part.
This bidirectional shift registeris designedto incorporate
virtuallyallofthe featuresa system designer may wantina
shift register.It features parallel inputs, parallel outputs,
right shiftandleft shift serial inputs, operating mode control
inputs,anda direct overriding clear line. The registerhas
four distinct modesof operation: PARALLEL (broadside)
LOAD; SHIFT RIGHT(inthe directionQA toward QD);
SHIFT LEFT; INHIBIT CLOCK(do nothing).
Synchronous parallel loadingis accomplishedby applying
thefourbitsof dataand taking both modecontrol inputs,S0
andS1, high. The dataare loadedinto their respectiveflip
flopsand appearatthe outputs afterthe positive transitionthe CLOCKinput. During loading, serial data flowis inhib-
ited. Shift rightis accomplished synchronously withtheris-
ing edgeofthe clock pulse whenS0is highandS1islow.
Serial dataforthis modeis enteredatthe SHIFT RIGHT
data input. WhenS0islowandS1is high, data shiftsleft
synchronouslyand new datais enteredatthe SHIFT LEFT
serial input. Clockingoftheflip flopsis inhibited when both
mode control inputsare low. The mode control inputs
shouldbe changed only whenthe CLOCK inputis high.
The 54HC/74HC logic familyis functionallyas wellaspin-
out compatible withthe standard 54LS/74LS logic family.
All inputsare protected from damage dueto static dis-
chargeby internal diode clampsto VCCand ground.
Features Typical operating frequency:45 MHz Typical propagation delay:ns (clocktoQ) Wide operating supply voltage range: 2–6V Low input current:1mA maximum Low quiescent supply current: 160 mA maximum
(74HC Series) Fanoutof10 LS-TTL loads
Connection Diagram Dual-In Line Package
TL/F/5323–1
Order Number MM54HC194or MM74HC194Function Table
Inputs Outputs
Mode Serial Parallel
ClearS1S2 Clock Left RightABCD QA QB QC QDX X X X XXXXL L L LX L X X XXXX QA0 QB0 QC0 QD0H u XX abcda b c dH u XHXXXXH QAn QBn QCnH u XL XXXXL QAn QBn QCnL u HX XXXX QBn QCn QDnHL u LX XXXX QBn QCn QDnLL X X X XXXX QA0 QB0 QC0 QD0ehighlevel (steady state)elowlevel (steady state)e irrelevant(any input, includingtransitions)e transitionfromlowtohighlevelb,c,dethelevelof steady-state inputat inputsA,B,C,orD,
respectively.
QA0,QB0,QC0,QD0ethelevelof QA,QB,QC,orQD, respectively,
beforethe indicatedsteady-stateinput conditions wereestablished.
QAn,QBn,QCn,QDnethelevelof QA,QB,QC, respectively, before
the most-recentu transitionofthe clock.
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
