MM74HC165MX ,Parallel-in/Serial-out 8-Bit Shift RegisterMM74HC165 Parallel-in/Serial-out 8-Bit Shift RegisterSeptember 1983Revised February 1999MM74HC165Pa ..
MM74HC165N ,Parallel-in/Serial-out 8-Bit Shift RegisterMM74HC165 Parallel-in/Serial-out 8-Bit Shift RegisterSeptember 1983Revised February 1999MM74HC165Pa ..
MM74HC165SJ ,Parallel-in/Serial-out 8-Bit Shift RegisterMM74HC165 Parallel-in/Serial-out 8-Bit Shift RegisterSeptember 1983Revised February 1999MM74HC165Pa ..
MM74HC174M ,Hex D-Type Flip-Flop with ClearMM74HC174 Hex D-Type Flip-Flops with ClearSeptember 1983Revised February 1999MM74HC174Hex D-Type Fl ..
MM74HC-174M ,Hex D-Type Flip-Flop with ClearGeneral Descriptionlent loads. The MM74HC174 is functionally as well as pinThe MM74HC174 edge trigg ..
MM74HC174MTC ,Hex D-Type Flip-Flop with ClearFeaturesmon clock and common clear. Data on the D input havingthe specified setup and hold times is ..
MN4SV17160BT-10 ,16M BIT SYNCHRONOUS DYNAMIC RAMapplications intended.(4) When designing your equipment, comply with the guaranteed values, inparti ..
MN5101 ,High-speed 8-bit A/D converterElectrical Characteristics (Ta=25°C)Maximum RatingsFunction .(Ta=25 c) Symbol Condition mm.hs----" ..
MN5121 , 8-bit A/D Converters
MN5123 , 8-bit A/D Converters
MN5141 , 8-bit A/D Converters
MN5177 ,Microcomputers Application-Specific Standard-Product ICsFor Video EquipmentMN5177Color Video Camera Synchronizing Signal Generator LSI Overview Pin Assignm ..
MM74HC165-MM74HC165M-MM74HC165MTCX-MM74HC165MTCX_NL-MM74HC165MX-MM74HC165N-MM74HC165SJ
Parallel-in/Serial-out 8-Bit Shift Register
MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register September 1983 Revised February 1999 MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register loading is inhibited as long as the SHIFT/LOAD input is General Description HIGH. When taken LOW, data at the parallel inputs is The MM74HC165 high speed PARALLEL-IN/SERIAL-OUT loaded directly into the register independent of the state of SHIFT REGISTER utilizes advanced silicon-gate CMOS the clock. technology. It has the low power consumption and high The 74HC logic family is functionally as well as pin-out noise immunity of standard CMOS integrated circuits, compatible with the standard 74LS logic family. All inputs along with the ability to drive 10 LS-TTL loads. are protected from damage due to static discharge by inter- This 8-bit serial shift register shifts data from Q to Q A H nal diode clamps to V and ground. CC when clocked. Parallel inputs to each stage are enabled by a low level at the SHIFT/LOAD input. Also included is a Features gated CLOCK input and a complementary output from the � Typical propagation delay: 20 ns (clock to Q) eighth bit. Clocking is accomplished through a 2-input NOR gate per- � Wide operating supply voltage range: 2–6V mitting one input to be used as a CLOCK INHIBIT function. � Low input current: 1 μA maximum Holding either of the CLOCK inputs high inhibits clocking, � Low quiescent supply current: 80 μA maximum (74HC and holding either CLOCK input low with the SHIFT/LOAD Series) input high enables the other CLOCK input. Data transfer � Fanout of 10 LS-TTL loads occurs on the positive going edge of the clock. Parallel Ordering Code: Order Number Package Number Package Description MM74HC165M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74HC165SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC165MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC165 N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Internal Output Pin Assignments for DIP, SOIC, SOP and TSSOP Shift/ Clock Parallel Q Clock Serial Outputs H A. . .H Q Q Load Inhibit A B LX X X a...ha b h HL L X X Q Q Q A0 B0 H0 HL ↑ HX HQ Q AN GN HL ↑ LX LQ Q AN GN HH X X X Q Q Q A0 B0 H0 H = HIGH Level (steady state), L = LOW Level (steady state) X = Irrelevant (any input, including transitions) ↑ = Transition from LOW-to-HIGH level Q , Q , Q = The level of Q , Q , or Q , respectively, before the indi- A0 B0 H0 A B H cated steady-state input conditions were established. Q , Q = The level of Q or Q before the most recent ↑ transition of the AN GN A G clock; indicates a one-bit shift. Top View © 1999 DS005316.prf
